本文整理汇总了Python中myhdl.Simulation类的典型用法代码示例。如果您正苦于以下问题：Python Simulation类的具体用法？Python Simulation怎么用？Python Simulation使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了Simulation类的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: testLatchOnEdge
def testLatchOnEdge(self):
""" Test DFF latches on clock rising edge """
q, d, clk = [Signal(0) for i in range(3)]
old_q, old_clk = [Signal(0) for i in range(2)]
clock_gen = ClkDriver(clk)
# change d longer than period so it will hold and change mid clock cycle
@always(delay(36))
def toggle():
d.next = not d
def testChange():
for i in range(200):
# check when no change in clock or falling edge
if clk == old_clk or clk == 0:
self.assertEqual(bool(q), bool(old_q))
# check for rising edge
else:
self.assertEqual(bool(q), bool(d))
old_q.next = q
old_clk.next = clk
yield delay(2)
flip_flop = dff(q, d, clk)
check = testChange()
sim = Simulation(clock_gen, flip_flop, check, toggle)
sim.run(200, quiet=1)示例2: main_simulate
def main_simulate():
resetn = Signal(bool(1))
system_clock = Signal(bool(0))
paddr = Signal(intbv(0, 0, 2**32))
psel = Signal(bool(0))
penable = Signal(bool(0))
pwrite = Signal(bool(1))
pwdata = Signal(intbv(0, 0, 2**32))
pready = Signal(bool(0))
prdata = Signal(intbv(0, 0, 2**32))
pslverr = Signal(bool(0))
apb3_bus_signals = [system_clock, resetn, paddr, psel, penable, pwrite,
pwdata, pready, prdata, pslverr]
SYSTEM_CLOCK_FREQ = 10e6
SYSTEM_CLOCK_PERIOD_IN_NS = int(1.0 / SYSTEM_CLOCK_FREQ * 1e9)
def testbench():
clock = drive_system_clock(system_clock, SYSTEM_CLOCK_PERIOD_IN_NS)
reset = drive_reset(resetn)
master = apb3_master_mock([(0x40050400, 0xffffffff),
(0x40050400, 0xffff7fff)],
*apb3_bus_signals)
slave = fluidsp_controller(*(apb3_bus_signals))
return clock, reset, slave, master
traced_testbench = traceSignals(testbench)
sim = Simulation(traced_testbench)
sim.run(SYSTEM_CLOCK_PERIOD_IN_NS * 100)示例3: test_lcounter
def test_lcounter(self):
def bench():
clk = Signal(False)
lzero = Signal(True)
lc = lcounter(clk, lzero)
@instance
def drive_stuff():
clk.next = 0
for j in range(2):
for i in range((1 << LCOUNT_BITS) - 1):
yield delay(1)
clk.next = 1
yield delay(1)
clk.next = 0
self.assertEqual(lzero, 0)
yield delay(1)
clk.next = 1
yield delay(1)
clk.next = 0
self.assertEqual(lzero, 1)
return (lc, drive_stuff)
tb = bench()
sim = Simulation(tb)
sim.run()示例4: run_sim
def run_sim():
# inst = traceSignals(env)
inst = env()
sim = Simulation(inst)
sim.run(40000000)
write_image()示例5: testLoad
def testLoad(self):
""" Test a Register load from 1 to 7 bits, always enabled """
for i in range(1, 8):
clk = Signal(0)
clock_gen = ClkDriver(clk, period=4)
#print "Testing", i, "bits"
out = Signal(intbv(0)[i:])
data = Signal(intbv(2**i - 1)[i:])
en = Signal(1)
reg = Register(out, data, clk, en)
flag = Signal(0)
# make sure it gets register value updated
@always(clk.posedge)
def test():
# need to delay by one
if flag == 1:
self.assertEqual(int(out), int(data))
else:
flag.next = 1
sim = Simulation(reg, clock_gen, test)
sim.run(20, quiet=1)示例6: test_jump
def test_jump(self):
dlx_instance = dlx(program=os.path.join(ROOT, 'programs/test6.txt'), data_mem=self.data_mem, reg_mem=self.reg_mem, Clk=None)
def test():
yield delay(10)
self.assertEqual(self.reg_mem[5].val, 0)
yield delay(2)
self.assertEqual(self.reg_mem[3].val, 8)
yield delay(2)
self.assertEqual(self.reg_mem[5].val, 4)
yield delay(2)
self.assertEqual(self.reg_mem[2].val, -4)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 7)
yield delay(12)
self.assertEqual(self.reg_mem[5].val, 8)
yield delay(2)
self.assertEqual(self.reg_mem[2].val, 0)
yield delay(2)
self.assertEqual(self.reg_mem[31].val, 24)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 52)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 7)
check = test()
sim = Simulation(dlx_instance, check)
sim.run(60, quiet=True)示例7: testReset
def testReset(self):
""" Test the reset function of a 4-bit counter """
clk = Signal(0)
rst = Signal(1)
clock_gen = ClkDriver(clk, period=4)
out = Signal(intbv(0)[4:])
counter = Counter(out, clk, rst)
def test():
for i in range(200):
# count up to 9 then reset
if int(out) == 9:
rst.next = 0
yield delay(1)
self.assertEqual(int(out), 0)
# turn off reset next time
else:
rst.next = 1
yield delay(1)
check = test()
sim = Simulation(counter, clock_gen, check)
sim.run(400, quiet=1)示例8: sim
def sim():
insts = []
insts.append(traceSignals(gen, *args))
insts.append(stimuli())
sim = Simulation(insts)
sim.run(duration)
print
sys.stdout.flush()示例9: runTests
def runTests(self, test):
"""Helper method to run the actual tests."""
for w in range(1, MAX_WIDTH):
B = Signal(intbv(0)[w:])
G = Signal(intbv(0)[w:])
dut = bin2gray(B, G)
check = test(B, G)
sim = Simulation(dut, check)
sim.run(quiet=1)示例10: test_not_mem_read
def test_not_mem_read(self):
@instance
def test():
self.MemRead_ex.next = 0
yield delay(1)
self.assertEqual(int(self.Stall), 0)
sim = Simulation(self.detector_, test)
sim.run()示例11: main_simulate
def main_simulate():
inst = test_signalgenerator(*get_signals())
sim = Simulation(inst)
# sim.run(SYSTEM_CLOCK_PERIOD_IN_NS * 1000)
sim.run(0.01 * 1e9) # run for 1ms
fig = plt.figure()
ax = fig.add_subplot(111)
ax.plot(i_samples_times, i_samples, q_samples_times, q_samples)
fig.savefig("output.png")示例12: sim
def sim():
from myhdl import Simulation, traceSignals
import sys
test_inst = traceSignals(create_test)
sim = Simulation(test_inst)
sim.run(20000)
print
sys.stdout.flush()示例13: test_not_regwrite_wb
def test_not_regwrite_wb(self):
@instance
def test():
self.RegWrite_wb.next = 0
yield delay(1)
self.assertEqual(int(self.ForwardA), 0)
self.assertEqual(int(self.ForwardB), 0)
sim = Simulation(self.forwarding_, test)
sim.run()示例14: sim
def sim(self):
insts = []
insts.append(traceSignals(self.gen, *self.args))
insts += self.stimuli
sim = Simulation(insts)
sim.run(self.duration)
print
sys.stdout.flush()示例15: test_regfile
def test_regfile():
clk = Signal(bool(0))
reset = ResetSignal(0, active=bool(1), async=True)
size = 32
read_addr1, read_addr2 = Signal(intbv(0)[5:]), Signal(intbv(0)[5:])
write_addr = Signal(intbv(0)[5:])
write_data = Signal(intbv(0, min=-2**32, max=2**32-1))
read_data1, read_data2 = Signal(intbv(0, min=-2**32, max=2**32-1)), Signal(intbv(0, min=-2**32, max=2**32-1))
write_ctrl = Signal(bool(0))
reg_file = register_file(read_addr1, read_addr2, write_addr, write_data, read_data1, read_data2, write_ctrl, clk, reset, size)
@always(delay(10))
def tb_clk():
clk.next = not clk
@instance
def tb_dut():
for jj in range(100):
wrlist = []
yield clk.posedge
# Write random data
for ii in range(32):
dwrite = randrange(-2**32,2**32-1)
wrlist.append(dwrite)
write_addr.next = ii
write_data.next = dwrite
write_ctrl.next = True
yield clk.posedge
write_ctrl.next = False
yield clk.posedge
# Verify written data
for ii in range(32):
read_addr1.next = ii
randread = randrange(32)
read_addr2.next = randread
yield clk.posedge
assert read_data1 == wrlist[ii]
assert read_data2 == wrlist[randread]
raise StopSimulation
sim = Simulation(tb_clk, tb_dut, reg_file)
sim.run()