本文整理汇总了Python中myhdl.traceSignals函数的典型用法代码示例。如果您正苦于以下问题：Python traceSignals函数的具体用法？Python traceSignals怎么用？Python traceSignals使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了traceSignals函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: test_simulate
def test_simulate(self):
import myhdl
duration=1
def _sim():
pix = Add_shift_top(duration=duration)
pix_presetn = pix.presetn
pix_pclk = pix.pclk
pix_paddr = pix.paddr
pix_psel = pix.psel
pix_penable = pix.penable
pix_pwrite = pix.pwrite
pix_pwdata = pix.pwdata
pix_pready = pix.pready
pix_prdata = pix.prdata
pix_pslverr = pix.pslverr
@myhdl.instance
def __sim():
yield pix.reset()
yield pix.transmit(0x4000, 0x0110)
return __sim
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run(10000)示例2: TestBench
def TestBench(MCP3008Tester):
ch1 = Signal(intbv(0)[10:])
ch2 = Signal(intbv(0)[10:])
ch3 = Signal(intbv(0)[10:])
ch4 = Signal(intbv(0)[10:])
ch5 = Signal(intbv(0)[10:])
ch6 = Signal(intbv(0)[10:])
ch7 = Signal(intbv(0)[10:])
ch8 = Signal(intbv(0)[10:])
spi_clk = Signal(LOW)
spi_ss_n = Signal(HIGH)
spi_miso = Signal(LOW)
spi_mosi = Signal(LOW)
clk = Signal(LOW)
rst_n = Signal(HIGH)
MCP3008Driver_inst = traceSignals(MCP3008Driver,
ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)
MCP3008Tester_inst = MCP3008Tester(
ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8,
spi_clk, spi_ss_n, spi_miso, spi_mosi, clk, rst_n)
ClkGen_inst = ClkGen(clk)
return MCP3008Driver_inst, MCP3008Tester_inst, ClkGen_inst示例3: main_simulate
def main_simulate():
resetn = Signal(bool(1))
system_clock = Signal(bool(0))
paddr = Signal(intbv(0, 0, 2**32))
psel = Signal(bool(0))
penable = Signal(bool(0))
pwrite = Signal(bool(1))
pwdata = Signal(intbv(0, 0, 2**32))
pready = Signal(bool(0))
prdata = Signal(intbv(0, 0, 2**32))
pslverr = Signal(bool(0))
apb3_bus_signals = [system_clock, resetn, paddr, psel, penable, pwrite,
pwdata, pready, prdata, pslverr]
SYSTEM_CLOCK_FREQ = 10e6
SYSTEM_CLOCK_PERIOD_IN_NS = int(1.0 / SYSTEM_CLOCK_FREQ * 1e9)
def testbench():
clock = drive_system_clock(system_clock, SYSTEM_CLOCK_PERIOD_IN_NS)
reset = drive_reset(resetn)
master = apb3_master_mock([(0x40050400, 0xffffffff),
(0x40050400, 0xffff7fff)],
*apb3_bus_signals)
slave = fluidsp_controller(*(apb3_bus_signals))
return clock, reset, slave, master
traced_testbench = traceSignals(testbench)
sim = Simulation(traced_testbench)
sim.run(SYSTEM_CLOCK_PERIOD_IN_NS * 100)示例4: test_simulate
def test_simulate(self):
import myhdl
duration=1
def _sim():
bus = Apb3Bus(duration=duration)
bus_presetn = bus.presetn
bus_pclk = bus.pclk
bus_paddr = bus.paddr
bus_psel = bus.psel
bus_penable = bus.penable
bus_pwrite = bus.pwrite
bus_pwdata = bus.pwdata
bus_pready = bus.pready
bus_prdata = bus.prdata
bus_pslverr = bus.pslverr
@myhdl.instance
def __sim():
yield bus.reset()
yield bus.transmit(0x4000, 0x0110)
return __sim
s = myhdl.Simulation(myhdl.traceSignals(_sim))
s.run(10000)示例5: testBench
def testBench():
if not DEBUG:
datapath_i = traceSignals(pipeline) # () #toVHDL(datapath)
else:
datapath_i = pipeline()
return instances()示例6: sim
def sim():
insts = []
insts.append(traceSignals(gen, *args))
insts.append(stimuli())
sim = Simulation(insts)
sim.run(duration)
print
sys.stdout.flush()示例7: __call__
def __call__(self):
if self.trace:
#traceSignals.timescale = toMyHDL.timescale
traceSignals.name = self.name
gen = traceSignals(self.top, *self.args, **self.kwargs)
else:
gen = self.top(*self.args, **self.kwargs)
return gen示例8: sim
def sim():
from myhdl import Simulation, traceSignals
import sys
test_inst = traceSignals(create_test)
sim = Simulation(test_inst)
sim.run(20000)
print
sys.stdout.flush()示例9: sim
def sim(self):
insts = []
insts.append(traceSignals(self.gen, *self.args))
insts += self.stimuli
sim = Simulation(insts)
sim.run(self.duration)
print
sys.stdout.flush()示例10: testBench
def testBench():
if not DEBUG:
datapath_i = traceSignals(dlx) #() #toVHDL(datapath)
else:
datapath_i = dlx()
return instances()示例11: test_memory
def test_memory():
"""
Memory: Test load and R/W operations.
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()示例12: test_core
def test_core(hex_file, vcd):
"""
Core: Behavioral test for the RISCV core.
"""
if vcd:
vcd = traceSignals(core_testbench, hex_file,)
sim = Simulation(vcd)
else:
sim = Simulation(core_testbench(hex_file))
sim.run()示例13: test_cache
def test_cache():
"""
Cache: Test loading from memory
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()示例14: sim
def sim(visu = False):
try:
os.remove('_bench.vcd')
except Exception as e:
pass # just ignore, the file is probably not here.
fsm = traceSignals(testbench())
sim = Simulation(fsm)
sim.run()
if visu:
call(['gtkwave', '_bench.vcd'])示例15: main
def main():
args = cliparse()
if args.trace:
mosi, miso, sck, ss = Signals(bool(0), 4)
led = Signal(bool(0))
clock=Clock(0, frequency=50e6)
tb_fsm = traceSignals(tb,led, clock, mosi, miso, sck, ss, reset=None)
sim = Simulation(tb_fsm)
sim.run()
if args.build:
build(args)