Python myhdl.intbv函数代码示例

    def gen_internal(self):
        self.cur_count = Signal(intbv(0, 0, self.count + 1))
        self.cur_skip = Signal(intbv(0, 0, self.skip + 1))

        self.new_count = Signal(intbv(0, 0, self.count + 1))
        self.new_skip = Signal(intbv(0, 0, self.skip + 1))

        @always_comb
        def comb():
            self.new_count.next = self.cur_count
            self.new_skip.next = self.cur_skip

            if self.cur_skip != 0:
                self.new_skip.next = self.cur_skip - 1

            elif self.cur_count != self.count:
                if self.strobe:
                    self.new_count.next = self.cur_count + 1
                    self.new_skip.next = self.skip

        @always_seq(self.clk.posedge, self.rst)
        def seq():
            self.cur_count.next = self.new_count
            self.cur_skip.next = self.new_skip

        @always_comb
        def busy_comb():
            self.busy.next = 1
            if self.new_count != self.count and self.new_skip == 0:
                self.busy.next = 0

        return instances()

    def __init__(self, size=16, width=8):
        """
        """
        self.name = "fifobus{0}".format(_fb_num)

        # @todo: add write clock and read clock to the interface!
        # @todo: use longer names read, read_valid, read_data,
        # @todo: write, write_data, etc.!

        # all the data signals are from the perspective
        # of the FIFO being interfaced to.        
        self.clear = Signal(bool(0))           # fifo clear
        #self.wclk = None                      # write side clock
        self.wr = Signal(bool(0))              # write strobe to fifo
        self.wdata = Signal(intbv(0)[width:])  # fifo data in

        #self.rclk = None                      # read side clock
        self.rd = Signal(bool(0))              # fifo read strobe
        self.rdata = Signal(intbv(0)[width:])  # fifo data out
        self.rvld = Signal(bool(0))
        self.empty = Signal(bool(1))           # fifo empty
        self.full = Signal(bool(0))            # fifo full
        self.count = Signal(intbv(0, min=0, max=size+1))

        self.width = width
        self.size = size

        _add_bus(self, self.name)

def led_peripheral(glbl, regbus, leds, base_address=0x8240):
    """ LED memory-map peripheral
    This (rather silly) core will select different LED
    displays based on the memory-mapped select register.
    """

    ndrv = 3  # the number of different drivers
    regfile.base_address = base_address 
    
    clock, reset = glbl.clock, glbl.reset
    rleds = Signal(intbv(0)[len(leds):])

    # assign the LED port to the local register
    assign(leds, rleds)

    # memory-mapped registers
    greg = regbus.add(regfile, 'led')

    # led bus from each driver
    dled = Signals(intbv(0)[len(leds):0], ndrv)

    # instantiate different LED drivers
    led_insts = [None for _ in range(ndrv)]
    led_insts[0] = led_stroby(clock, reset, dled[0])
    led_insts[1] = led_count(clock, reset, dled[1])
    led_insts[2] = led_dance(clock, reset, dled[2])

    @always_seq(clock.posedge, reset=reset)
    def beh():
        for ii in range(ndrv):
            idx = regfile.select
            rleds.next = dled[idx-1]

    return myhdl.instances()

 def __init__(self, nbits=8):
     """member variables initialize"""
     self.nbits = nbits
     self.red = Signal(intbv(0)[nbits:])
     self.green = Signal(intbv(0)[nbits:])
     self.blue = Signal(intbv(0)[nbits:])
     self.data_valid = Signal(bool(0))

def uartRx(CLK, RST_X, RXD, DOUT, EN):

    # reg
    stage = myhdl.Signal(myhdl.intbv(0)[4:])
    cnt = myhdl.Signal(myhdl.intbv(0)[21:])                  # counter to latch D0, D1, ..., D7
    cnt_detect_startbit = myhdl.Signal(myhdl.intbv(0)[20:])  # counter to detect the Start Bit

    @myhdl.always_comb
    def assign():
        EN.next = (stage == SS_SER_DONE)

    @myhdl.always(CLK.posedge)
    def detect_startbit():
        if not RST_X:
            cnt_detect_startbit.next = 0
        else:
            cnt_detect_startbit.next = 0 if (RXD) else cnt_detect_startbit + 1

    @myhdl.always(CLK.posedge)
    def main_proc():
        if not RST_X:
            stage.next = SS_SER_WAIT
            cnt.next = 1
            DOUT.next = 0
        elif (stage == SS_SER_WAIT):
            stage.next = SS_SER_RCV0 if (cnt_detect_startbit == (SERIAL_WCNT >> 1)) else stage
        else:
            if (cnt != SERIAL_WCNT):
                cnt.next = cnt + 1
            else:
                stage.next = SS_SER_WAIT if (stage == SS_SER_DONE) else stage + 1
                DOUT.next = myhdl.ConcatSignal(RXD, DOUT[8:1])
                cnt.next = 1

    return assign, detect_startbit, main_proc

    def __init__(self, data_width=32,  address_width=4, response_width=2):
        self.data_width = data_width
        self.address_width = address_width
        self.response_width = response_width
        # currently top-level port interfaces can't contain multiple
        # levels (nested).  This will be enhanced in the future.

        self.awvalid = Signal(bool(0))
        self.awdata = Signal(intbv(15)[address_width:])
        self.awaccept = Signal(bool(1))

        self.wvalid = Signal(bool(0))
        self.wdata = Signal(intbv(0xE6)[data_width:])
        self.waccept = Signal(bool(1))

        self.arvalid = Signal(bool(0))
        self.ardata = Signal(intbv(15)[address_width:])
        self.araccept = Signal(bool(1))

        self.rvalid = Signal(bool(0))
        self.rdata = Signal(intbv(0xE8)[data_width:])
        self.raccept = Signal(bool(1))

        self.bvalid = Signal(bool(0))
        self.bdata = Signal(intbv(3)[response_width:])
        self.baccept = Signal(bool(1))

    def op_add_sub():

        if __debug__:
            if debug:
                print("inside alu", acc, opd)
        if dec.add_sub == 0:
            res_arith.next = intbv(acc + opd)[16:]
            if __debug__:
                if debug:
                    print(res_arith.next, acc + opd, acc, opd)
        else:
            res_arith.next = intbv(acc - opd)[16:]

    # for the logical operations
    # @always_comb
    # def op_logical():

        if alu_op == alu_op_type.LD:
            # LOAD
            res_log.next = opd

        elif alu_op == alu_op_type.AND:
            # AND
            res_log.next = acc & opd

        elif alu_op == alu_op_type.OR:
            # OR
            res_log.next = acc | opd

        elif alu_op == alu_op_type.XOR:
            # XOR
            res_log.next = acc ^ opd

    def gen(self):
        idx = Signal(intbv(0, 0, self.parts))

        insts = []

        rd_parts = []
        for i in range(self.parts):
            s = Signal(intbv(0)[self.data_width:])
            insts.append(self.extract(s, i))
            rd_parts.append(s)

        @always_comb
        def comb():
            self.parent.RD.next = 0
            self.RD_DATA.next = rd_parts[idx]
            self.RD_EMPTY.next = self.parent.RD_EMPTY

            if self.RD and idx == self.parts - 1:
                self.parent.RD.next = 1

        @always_seq(self.RD_CLK.posedge, self.RD_RST)
        def seq():
            if self.RD:
                idx.next = 0
                if idx != self.parts - 1:
                    idx.next = idx + 1

        return instances()

def convert():
    clock = Signal(bool(0))
    addr = Signal(intbv(0)[8:])
    datao = Signal(intbv(0)[16:])
    inst = romr(addr, clock, datao)
    inst.convert(hdl='Verilog', name='ROMR',
                 directory='output_files', testbench=False)

def serial_adder(R, load_en, clk, add_carry):
    '''
    adds the two numbers given in R and stores the sum in
    the lower significant half of R
    :param R: Two numbers of equal bit vector length
    :param load_en: when equal to 1 it parallel loads the value in R to the two internal shift registers
    :param clk:
    :param add_carry: will contain the final carry bit after adding the msbs
    '''
    out1 = Signal(intbv(0)[len(R)/2:])
    parallelin1 = R[len(R):len(R)/2]
    out2 = Signal(intbv(0)[len(R)/2:])
    parallelin2 = R[len(R)/2:]
    sum, cin, cout, inp1, inp2, a, b = [Signal(intbv(0)) for i in range(7)]
    shift1 = shift_reg(inp1, out1, clk, parallelin1, load_en)    #contains first number
    shift2 = shift_reg(inp2,out2,clk,parallelin2, load_en)       #contains second number initially and final result at the end of simulation
    adder = full_adder(a, b, cin, sum, cout, clk)
    @always_comb
    def connect():
        inp1.next = intbv(out1[0])[1:]
        inp2.next = sum
        a.next = intbv(out1[0])[1:]
        b.next = intbv(out2[0])[1:]
        add_carry.next = cout
    return connect, shift1, shift2, adder

    def mux_test():

        sel    = Signal(bool(0))
        q      = Signal(intbv(0))
        a      = Signal(intbv(0))
        b      = Signal(intbv(0))

        mux = mux2(q, a, b, sel)

        DELAY = delay(PERIOD // 2)

        @instance
        def stimulus():
            for step in range(STEPS):
                print "STEP %02d:" % step,

                a.next = step
                b.next = step << 8

                if step % 2 == 0:
                    sel.next = not sel

                yield DELAY
                print "%d q %s a %s b %s" % (sel, bin(q, 16), bin(a, 16), bin(b, 16))
                if sel % 2 == 0:
                    assert q == a
                else:
                    assert q == b

            raise StopSimulation

        return mux, stimulus

def convert():
    q = Signal(intbv(0)[1:0])
    d = Signal(intbv(0)[1:0])
    wr, rst = [Signal(bool(0)) for i in range(2)]

    toVerilog(dff, q, d, wr, rst)
    toVHDL(dff, q, d, wr, rst)

 def __init__(self, color_space=(8, 8, 8)):
     """An red-green-blue interface """
     assert len(color_space) == 3
     rbits, gbits, bbits = color_space
     self.red = Signal(intbv(0)[rbits:0])
     self.green = Signal(intbv(0)[gbits:0])
     self.blue = Signal(intbv(0)[rbits:0])

def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr, uart_rts):
    """
    This example is similar to the other examples in this directory but
    the LEDs are controlled externally via command packets sent from a
    host via the UART on the icestick.

    Ports:
      clock:
      led:
      pmod:
      uart_tx:
      uart_rx:
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fbustx = FIFOBus(width=8, size=4)
    fbusrx = FIFOBus(width=8, size=4)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, uart_tx)

    # create the packet command instance
    cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)

    @always_seq(clock.posedge, reset=None)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]

        pmod.next = 0

    # @todo: PMOD OLED memmap control

    return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read, beh_assign)

def emit_connect():
    from myhdl import toVerilog

    bus = DdrBus(2, 12, 2)
    rename_interface(bus, 'bus')

    soc_clk = Signal(False)
    soc_clk_b = Signal(False)

    soc_cs = Signal(False)
    soc_ras = Signal(False)
    soc_cas = Signal(False)
    soc_we = Signal(False)
    soc_ba = Signal(False)
    soc_a = Signal(False)

    soc_dqs = Signal(intbv(0)[bus.d_width:])
    soc_dm = Signal(intbv(0)[bus.d_width:])
    soc_dq = Signal(intbv(0)[bus.d_width * 8:])

    toVerilog(ddr_connect, bus, soc_clk, soc_clk_b, None,
              soc_cs, soc_ras, soc_cas, soc_we, soc_ba, soc_a,
              soc_dqs, soc_dm, soc_dq)

    print
    print open('ddr_connect.v', 'r').read()