Python myhdl.instances函数代码示例

def UIntToFloat(
        float_output,
        uint_input,
        exponent_width,
        fraction_width,
        exponent_bias
    ):
    
    # Calculating unbiased and biased exponent.
    unbiased_exponent = Signal(modbv(0)[exponent_width:])
    biased_exponent = Signal(modbv(0)[exponent_width:])
    nz_flag = Signal(bool(0))
    unbiased_exponent_calculator = PriorityEncoder(
            unbiased_exponent, nz_flag, uint_input)
    @always_comb
    def biased_exponent_calculator():
        biased_exponent.next = unbiased_exponent + exponent_bias
    
    # Calculating fraction part. 
    fraction = Signal(modbv(0)[fraction_width:])
    fraction_calculator = UIntToFraction(
            fraction, uint_input, unbiased_exponent)
    
    float_sig = ConcatSignal(bool(0), biased_exponent, fraction)
    
    @always_comb
    def make_output():
        if uint_input == 0:
            float_output.next = 0
        else:
            float_output.next = float_sig
        
            
    return instances()

    def gen(self):
        system0 = self.system0
        bus0 = self.bus0()

        ram = [ Signal(intbv(0)[self.data_width:])
                for _ in range(self.addr_depth) ]

        @always_seq(system0.CLK.posedge, system0.RST)
        def seq0():
            if bus0.WR:
                ram[bus0.ADDR].next = bus0.WR_DATA

            if bus0.RD and bus0.ADDR < len(ram):
                bus0.RD_DATA.next = ram[bus0.ADDR]
            else:
                bus0.RD_DATA.next = 0

        system1 = self.system1
        bus1 = self.bus1()

        @always_seq(system1.CLK.posedge, system1.RST)
        def seq1():
            if bus1.WR:
                ram[bus1.ADDR].next = bus1.WR_DATA

            if bus1.RD and bus1.ADDR < len(ram):
                bus1.RD_DATA.next = ram[bus1.ADDR]
            else:
                bus1.RD_DATA.next = 0

        return instances()

def xula_vga(
    # ~~~[PORTS]~~~
    vselect,
    hsync, vsync, 
    red, green, blue,
    pxlen, active,
    clock,
    reset=None,

    # ~~~~[PARAMETERS]~~~~
    # @todo: replace these parameters with a single VGATimingParameter
    resolution=(640, 480,),
    color_depth=(8, 8, 8,),
    refresh_rate=60,
    line_rate=31250
):
    """
    (arguments == ports)
    Arguments:
        vselect:

    Parameters:
        resolution: the video resolution
        color_depth: the color depth of a pixel, the number of bits
            for each color component in a pixel.
        refresh_rate: the refresh rate of the video
    """
    # stub out reset if needed
    if reset is None:
        reset = ResetSignal(0, active=0, async=False)

        @always(clock.posedge)
        def reset_stub():
            reset.next = not reset.active

    else:
        reset_stub = None

    # create the system-level signals, overwrite clock, reset
    glbl = Global(clock=clock, reset=reset)

    # VGA inteface
    vga = VGA()
    # assign the top-level ports to the VGA interface
    vga.assign(
        hsync=hsync, vsync=vsync,
        red=red, green=green, blue=blue,
        pxlen=pxlen, active=active
    )

    # video memory interface
    vmem = VideoMemory(color_depth=color_depth)
        
    # color bar generation
    bar_inst = color_bars(glbl, vmem, resolution=resolution)

    # VGA driver
    vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)

    return myhdl.instances()

def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbusrtx = FIFOBus(width=8)

    # get the UART comm from PC
    uart_inst = uartlite(glbl, fbusrtx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrtx.write_data.next = fbusrtx.read_data
        fbusrtx.write.next = (not fbusrtx.full) & fbusrtx.read

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return myhdl.instances()

def depp(clock,a_dstb,a_astb,a_write,a_wait,a_addr_reg,a_db,to_rpi2B):

    @always_comb
    def rtl1():
        a_wait.next = not a_astb or not a_dstb

    @always(clock.posedge)
    def rtl2():
        a_astb_sr.next = concat(a_astb_sr[2:0], a_astb)
        a_dstb_sr.next = concat(a_dstb_sr[2:0], a_dstb)

    @always(clock.posedge)
    def rtl3():
        if (~a_write and a_astb_sr == 4):
            a_addr_reg.next = a_db

    @always(clock.posedge)
    def rtl4():
        if (~a_write and a_dstb_sr == 4):
            a_data_reg.next = a_db

    @always_comb
    def rtl5():
	if(a_write == 1):
            to_rpi2B.next = a_data_reg

    return myhdl.instances()

def DualDelayer(
        timeout_short,
        timeout_long,
        clk,
        rst,
        interval_short, # Parameter (Seconds)
        interval_long,  # Parameter (Seconds)
        clk_freq, # Parameter (Hz)
    ):
    COUNTER_LONG_MAX  = int(interval_long  * clk_freq)
    COUNTER_SHORT_MAX = int(interval_short * clk_freq) 

    counter = Signal(intbv(0, min=0, max=COUNTER_LONG_MAX+1))

    @always(clk.posedge, rst.posedge)
    def do():
        if rst:
            counter.next = 0
            timeout_short.next = 0
            timeout_long.next = 0
        else:
            if counter >= COUNTER_SHORT_MAX:
                timeout_short.next = 1
            else:
                timeout_short.next = 0
            if counter >= COUNTER_LONG_MAX:
                timeout_long.next = 1
            else:
                timeout_long.next = 0
                counter.next = counter + 1

    return instances()

    def gen(self):
        system = self.system
        bus = self.bus()

        mem = [ Signal(intbv(0)[self.accumulator_width:])
                for _ in range(1<<self.sample_width) ]

        inc = Signal(False)
        inc_idx = Signal(intbv(0)[self.sample_width:])
        inc_val = Signal(intbv(0)[self.accumulator_width:])

        @always_seq(system.CLK.posedge, system.RST)
        def contributions_inst():
            bus.RD_DATA.next = 0

            if bus.WR:
                mem[bus.ADDR].next = bus.WR_DATA
            elif inc:
                inc.next = 0
                mem[inc_idx].next = inc_val

            if bus.RD:
                bus.RD_DATA.next = mem[bus.ADDR]
            elif self.STROBE:
                inc.next = 1
                inc_idx.next = self.SAMPLE
                inc_val.next = mem[self.SAMPLE].next + 1

        return instances()

def Test():
    depth = 4
    width = 4
    
    dout = Signal(modbv(0)[width:])
    din = Signal(modbv(0)[width:])
    full = Signal(bool(0))
    empty = Signal(bool(0))
    push = Signal(bool(0))
    clk = Signal(bool(0))
    
    stack = Stack(dout, din, full, empty, push, clk, width=width, depth=depth)
    
    @instance
    def stimulus():
        print('dout\tdin\tfull\tempty\tpush')
        push.next = 1
        for k in range(16):
            din.next = k + 1
            push.next = k < 8
            yield delay(10)
            clk.next = 1
            yield delay(10)
            clk.next = 0
            print(dout, din, full, empty, push, sep='\t')
            
    return instances()

def toplevel(i_clk, i_rpi2B,fr_depp,o_rpi2B,to_depp):
    dut_rpi2B_io = rpi2B_io(i_rpi2B,o_depp,o_rpi2B,to_depp)
    reset_dly_cnt = Signal(intbv(0)[5:])
    @always(i_clk.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 0
            if (reset_dly_cnt >= 5):
                reset.next = 1
                #i_int.next = 1
        else:
            reset.next = 0
 
    

    dut_my_wbdepp = my_wbdepp(i_clk,i_astb_n,i_dstb_n,i_write_n,to_depp,\
    fr_depp,o_wait,o_wb_cyc,o_wb_stb, \
    o_wb_we,o_wb_addr,o_wb_data,i_wb_ack,i_wb_stall,i_wb_err,i_wb_data,i_int)
      
    return myhdl.instances()

def testBench_alu():

    control_i = Signal(intbv(0)[4:])

    op1_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
    op2_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))

    out_i = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))

    zero_i = Signal(bool(False))

    alu_i = ALU(control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = toVHDL(ALU, control_i, op1_i, op2_i, out_i, zero_i)
    #alu_i = analyze(alu, control_i, op1_i, op2_i, out_i, zero_i)

    control_func = (('0000', 'AND'), ('0001', 'OR'), ('0010', 'add'), ('0110', 'substract'), ('0111', '<'), ('1100', 'NOR'))

    @instance
    def stimulus():
        for control_val, func in [(int(b, 2), func) for (b, func) in control_func]:
            control_i.next = Signal(intbv(control_val))

            op1_i.next, op2_i.next = [intbv(random.randint(0, 255))[32:] for i in range(2)]

            yield delay(10)
            print "Control: %s | %i %s %i | %i | z=%i" % (bin(control_i, 4), op1_i, func, op2_i, out_i, zero_i)

    return instances()

def Stack(dout, din, full, empty, push, clk, posedge=True, width=8, depth=128):
    mem = [Signal(intbv(0)[width:]) for i in range(depth)]
    pointer = Signal(modbv(0, min=0, max=depth))
    
    if posedge:
        edge = clk.posedge
    else:
        edge = clk.negedge

    @always_seq(edge, reset=None)
    def operate():
        if push:
            if pointer == depth - 1:
                full.next = True
                empty.next = False
            if not full:
                mem[pointer].next = din
                pointer.next = pointer + 1                
        else:
            if pointer == 1:
                empty.next = True
                full.next = False
            if not empty:
                dout.next = mem[pointer-1]
                pointer.next = pointer - 1

    return instances()

def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    gticks = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbustx = FIFOBus(width=8, size=8)
    fbusrx = FIFOBus(width=8, size=8)

    # get the UART comm from PC
    guart = uartlite(glbl, fbustx, fbusrx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrx.rd.next = not fbusrx.empty
        fbustx.wr.next = not fbusrx.empty
        fbustx.wdata.next = fbusrx.rdata

    lcnt = Signal(modbv(0, min=0, max=4))
    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return instances()

def test_video_interface():

    # resolution of the video is kept low to reduce simulation time
    res = (50, 50)

    # a sample pixel
    pixel = [1, 0, 0]

    clock = Signal(bool(0))
    clock_drive = clock_driver(clock)

    video_interface = VideoInterface(clock, res)

    @instance
    def test():

        video_interface.reset_cursor()
        yield video_interface.enable_video()

        # iterating over the frame
        for _ in range(res[0]*res[1]):
            # Sending a pixel
            yield video_interface.write_pixel(pixel), \
                video_interface.read_pixel()
            assert video_interface.get_pixel() == pixel

        yield video_interface.disable_video()

    return instances()

def IntToFloat(
        float_output,
        int_input,
        exponent_width,
        fraction_width,
        exponent_bias):
    INT_WIDTH = len(int_input)
    FLOAT_WIDTH = len(float_output)
    
    sign = Signal(bool(0))
    sign_getter = SignGetter(sign, int_input)
    
    abs_int = Signal(modbv(0)[INT_WIDTH:])           
    abs_calculator = Abs(abs_int, int_input)
    
    abs_float = Signal(modbv(0)[(1+exponent_width+fraction_width):])         
    float_calculator = UIntToFloat(
            abs_float, abs_int, 
            exponent_width, fraction_width, exponent_bias)
    
    signed_float = ConcatSignal(sign, abs_float(FLOAT_WIDTH-1, 0))
    
    @always_comb
    def make_output():
        float_output.next = signed_float
        
    return instances()

def rst_sync(clk, rst_in, rst_out, n = 2):
    taps = [ Signal(False) for _ in range(n) ]

    @always(clk.posedge, rst_in.posedge)
    def rst_seq():
        if rst_in:
            for i in range(0, len(taps)):
                taps[i].next = 0
        else:
            for i in range(1, len(taps)):
                taps[i].next = taps[i-1]
            taps[0].next = 1

    if isinstance(rst_out, ResetSignal):
        active = rst_out.active
    else:
        active = 1

    @always_comb
    def rst_comb():
        if taps[len(taps)-1]:
            rst_out.next = not active
        else:
            rst_out.next = active

    return instances()