本文整理汇总了Python中migen.genlib.record.Record类的典型用法代码示例。如果您正苦于以下问题：Python Record类的具体用法？Python Record怎么用？Python Record使用的例子？那么恭喜您, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了Record类的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: __init__
def __init__(self, interface, counter, fifo_depth):
data_width = rtlink.get_data_width(interface)
fine_ts_width = rtlink.get_fine_ts_width(interface)
ev_layout = []
if data_width:
ev_layout.append(("data", data_width))
if interface.timestamped:
ev_layout.append(("timestamp", counter.width + fine_ts_width))
self.ev = Record(ev_layout)
self.readable = Signal()
self.re = Signal()
self.overflow = Signal() # pulsed
# # #
fifo = ClockDomainsRenamer({"read": "rsys", "write": "rio"})(
AsyncFIFO(layout_len(ev_layout), fifo_depth))
self.submodules += fifo
fifo_in = Record(ev_layout)
fifo_out = Record(ev_layout)
self.comb += [
fifo.din.eq(fifo_in.raw_bits()),
fifo_out.raw_bits().eq(fifo.dout)
]
# latency compensation
if interface.delay:
counter_rtio = Signal.like(counter.value_rtio, reset_less=True)
self.sync.rtio += counter_rtio.eq(counter.value_rtio -
(interface.delay + 1))
else:
counter_rtio = counter.value_rtio
# FIFO write
if data_width:
self.comb += fifo_in.data.eq(interface.data)
if interface.timestamped:
if fine_ts_width:
full_ts = Cat(interface.fine_ts, counter_rtio)
else:
full_ts = counter_rtio
self.comb += fifo_in.timestamp.eq(full_ts)
self.comb += fifo.we.eq(interface.stb)
# FIFO read
self.comb += [
self.ev.eq(fifo_out),
self.readable.eq(fifo.readable),
fifo.re.eq(self.re)
]
overflow_transfer = BlindTransfer()
self.submodules += overflow_transfer
self.comb += [
overflow_transfer.i.eq(fifo.we & ~fifo.writable),
self.overflow.eq(overflow_transfer.o),
]示例2: __init__
def __init__(self):
self.sink = Sink(ULPI_DATA_D)
self.source = Source(ULPI_DATA_D)
valid = Signal()
data = Record(ULPI_DATA_D)
self.comb += [
If(self.sink.stb,
self.sink.ack.eq(1),
)]
self.sync += [
If(self.sink.stb,
valid.eq(1),
If(valid & ~self.source.ack,
data.rxcmd.eq(1),
data.d.eq(RXCMD_MAGIC_OVF),
).Else(
data.eq(self.sink.payload)
)
).Elif(self.source.ack,
valid.eq(0)
)]
self.comb += [
self.source.stb.eq(valid),
self.source.payload.eq(data)
]示例3: __init__
def __init__(self, nchan=3, depth=8):
self.valid_i = Signal()
self.chan_synced = Signal()
self._r_channels_synced = CSRStatus()
lst_control = []
all_control = Signal()
for i in range(nchan):
name = "data_in" + str(i)
data_in = Record(channel_layout, name=name)
setattr(self, name, data_in)
name = "data_out" + str(i)
data_out = Record(channel_layout, name=name)
setattr(self, name, data_out)
###
syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
self.submodules += syncbuffer
self.comb += [syncbuffer.din.eq(data_in.raw_bits()), data_out.raw_bits().eq(syncbuffer.dout)]
is_control = Signal()
self.comb += [is_control.eq(~data_out.de), syncbuffer.re.eq(~is_control | all_control)]
lst_control.append(is_control)
some_control = Signal()
self.comb += [all_control.eq(optree("&", lst_control)), some_control.eq(optree("|", lst_control))]
self.sync.pix += If(~self.valid_i, self.chan_synced.eq(0)).Else(
If(some_control, If(all_control, self.chan_synced.eq(1)).Else(self.chan_synced.eq(0)))
)
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)示例4: __init__
def __init__(self, interface, counter, fifo_depth):
data_width = rtlink.get_data_width(interface)
fine_ts_width = rtlink.get_fine_ts_width(interface)
ev_layout = []
if data_width:
ev_layout.append(("data", data_width))
if interface.timestamped:
ev_layout.append(("timestamp", counter.width + fine_ts_width))
self.ev = Record(ev_layout)
self.readable = Signal()
self.re = Signal()
self.overflow = Signal() # pulsed
# # #
fifo = ClockDomainsRenamer({"read": "rsys", "write": "rio"})(
AsyncFIFO(layout_len(ev_layout), fifo_depth))
self.submodules += fifo
fifo_in = Record(ev_layout)
fifo_out = Record(ev_layout)
self.comb += [
fifo.din.eq(fifo_in.raw_bits()),
fifo_out.raw_bits().eq(fifo.dout)
]
# FIFO write
if data_width:
self.comb += fifo_in.data.eq(interface.data)
if interface.timestamped:
if fine_ts_width:
full_ts = Cat(interface.fine_ts, counter.value_rio)
else:
full_ts = counter.value_rio
self.comb += fifo_in.timestamp.eq(full_ts)
self.comb += fifo.we.eq(interface.stb)
# FIFO read
self.comb += [
self.ev.eq(fifo_out),
self.readable.eq(fifo.readable),
fifo.re.eq(self.re)
]
overflow_sync = PulseSynchronizer("rio", "rsys")
overflow_ack_sync = PulseSynchronizer("rsys", "rio")
self.submodules += overflow_sync, overflow_ack_sync
overflow_blind = Signal()
self.comb += overflow_sync.i.eq(fifo.we & ~fifo.writable & ~overflow_blind)
self.sync.rio += [
If(fifo.we & ~fifo.writable, overflow_blind.eq(1)),
If(overflow_ack_sync.o, overflow_blind.eq(0))
]
self.comb += [
overflow_ack_sync.i.eq(overflow_sync.o),
self.overflow.eq(overflow_sync.o)
]示例5: __init__
def __init__(self, port, lasmim_dma_wr, lasmim_dma_rd):
self.submodules.writer = LiteUSBDMAWriter(lasmim_dma_wr)
self.submodules.reader = LiteUSBDMAReader(lasmim_dma_rd, port.tag)
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
self.comb += [
Record.connect(port.source, self.writer.sink),
Record.connect(self.reader.source, port.sink),
]示例6: __init__
def __init__(self):
self.busy = Signal()
self.sink = Sink(CMD_REC)
self.source = Source([('d',8), ('last',1)])
sm = FSM(reset_state="IDLE")
self.submodules += sm
self.comb += [
self.source.stb.eq(0),
self.source.payload.last.eq(0)
]
ssum = Signal(8)
token_next = Record(CMD_REC)
token = Record(CMD_REC)
self.comb += token_next.eq(token)
self.sync += token.eq(token_next)
sm.act("IDLE",
If(self.sink.stb,
self.sink.ack.eq(1),
token_next.eq(self.sink.payload),
NextState('c0')))
_outs = [
0x55,
Cat(token.a[8:14], 0, token.wr),
token.a[0:8],
token.d,
ssum
]
s = _outs[0]
for i in _outs[1:-1]:
s = s + i
self.sync += ssum.eq(s)
for c, v in enumerate(_outs):
_last = 1 if c == len(_outs) - 1 else 0
_next = "IDLE" if _last else "c%d" % (c + 1)
sm.act("c%d" % c,
self.source.stb.eq(1),
self.source.payload.d.eq(v),
self.source.payload.last.eq(_last),
If(self.source.ack,
NextState(_next)
))示例7: __init__
def __init__(self, stream_slicer):
self.source = stream.Endpoint(record_layout)
self.end_marker_found = Signal()
self.flush = Signal()
hdrlen = (layout_len(record_layout) - 512)//8
record_raw = Record(record_layout)
self.comb += [
record_raw.raw_bits().eq(stream_slicer.source),
self.source.channel.eq(record_raw.channel),
self.source.timestamp.eq(record_raw.timestamp),
self.source.address.eq(record_raw.address),
Case(record_raw.length,
{hdrlen+i: self.source.data.eq(record_raw.data[:i*8])
for i in range(1, 512//8+1)}),
]
fsm = FSM(reset_state="FLOWING")
self.submodules += fsm
fsm.act("FLOWING",
If(stream_slicer.source_stb,
If(record_raw.length == 0,
NextState("END_MARKER_FOUND")
).Else(
self.source.stb.eq(1)
)
),
If(self.source.ack,
stream_slicer.source_consume.eq(record_raw.length)
)
)
fsm.act("END_MARKER_FOUND",
self.end_marker_found.eq(1),
If(self.flush,
stream_slicer.flush.eq(1),
NextState("WAIT_FLUSH")
)
)
fsm.act("WAIT_FLUSH",
If(stream_slicer.flush_done,
NextState("SEND_EOP")
)
)
fsm.act("SEND_EOP",
self.source.eop.eq(1),
self.source.stb.eq(1),
If(self.source.ack, NextState("FLOWING"))
)示例8: DownscalerCore
class DownscalerCore(Module):
def __init__(self, base_layout, N, res_bits):
self.init = Signal()
self.ready = Signal()
self.ce = Signal()
self.hres_in = Signal(res_bits)
self.vres_in = Signal(res_bits)
self.i = Record([("w"+str(i), base_layout) for i in range(N)])
self.hres_out = Signal(res_bits)
self.vres_out = Signal(res_bits)
self.o = Record([("w"+str(i), base_layout) for i in range(N)])
self.stb = Signal()
###
packbits = log2_int(N)
hcounter = Signal(res_bits-packbits)
self.sync += If(self.init,
hcounter.eq(self.hres_in[packbits:] - 1)
).Elif(self.ce,
If(hcounter == 0,
hcounter.eq(self.hres_in[packbits:] - 1)
).Else(
hcounter.eq(hcounter - 1)
)
)
self.submodules.vselector = InsertReset(InsertCE(Chopper(res_bits)))
self.comb += [
self.vselector.reset.eq(self.init),
self.vselector.ce.eq(self.ce & (hcounter == 0)),
self.vselector.p.eq(self.vres_out),
self.vselector.q.eq(self.vres_in)
]
self.submodules.hselector = MultiChopper(N, res_bits)
self.comb += [
self.hselector.init.eq(self.init),
self.ready.eq(self.hselector.ready),
self.hselector.next.eq(self.ce),
self.hselector.p.eq(self.hres_out),
self.hselector.q.eq(self.hres_in)
]
self.submodules.compacter = InsertReset(InsertCE(Compacter(base_layout, N)))
self.submodules.packer = InsertReset(InsertCE(Packer(base_layout, N)))
self.comb += [
self.compacter.reset.eq(self.init),
self.packer.reset.eq(self.init),
self.compacter.ce.eq(self.ce),
self.packer.ce.eq(self.ce),
self.compacter.i.eq(self.i),
self.compacter.sel.eq(self.hselector.chopper & Replicate(self.vselector.chopper, N)),
self.packer.i.eq(self.compacter.o),
self.packer.count.eq(self.compacter.count),
self.o.eq(self.packer.o),
self.stb.eq(self.packer.stb)
]示例9: __init__
def __init__(self, nimages, pack_factor, latency):
epixel_layout = pixel_layout(pack_factor)
sink_layout = [("i"+str(i), epixel_layout) for i in range(nimages)]
self.sink = Sink(sink_layout)
self.source = Source(epixel_layout)
factors = []
for i in range(nimages):
name = "f"+str(i)
csr = CSRStorage(8, name=name)
setattr(self, name, csr)
factors.append(csr.storage)
PipelinedActor.__init__(self, latency)
###
sink_registered = Record(sink_layout)
self.sync += If(self.pipe_ce, sink_registered.eq(self.sink.payload))
imgs = [getattr(sink_registered, "i"+str(i)) for i in range(nimages)]
outval = Record(epixel_layout)
for e in epixel_layout:
name = e[0]
inpixs = [getattr(img, name) for img in imgs]
outpix = getattr(outval, name)
for component in ["r", "g", "b"]:
incomps = [getattr(pix, component) for pix in inpixs]
outcomp = getattr(outpix, component)
outcomp_full = Signal(19)
self.comb += [
outcomp_full.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors))),
If(outcomp_full[18],
outcomp.eq(2**10 - 1) # saturate on overflow
).Else(
outcomp.eq(outcomp_full[8:18])
)
]
pipe_stmts = []
for i in range(latency-1):
new_outval = Record(epixel_layout)
pipe_stmts.append(new_outval.eq(outval))
outval = new_outval
self.sync += If(self.pipe_ce, pipe_stmts)
self.comb += self.source.payload.eq(outval)示例10: __init__
def __init__(self, phy,
tx_fifo_depth=16,
rx_fifo_depth=16,
phy_cd="sys"):
self._rxtx = CSR(8)
self._txfull = CSRStatus()
self._rxempty = CSRStatus()
self.submodules.ev = EventManager()
self.ev.tx = EventSourceProcess()
self.ev.rx = EventSourceProcess()
self.ev.finalize()
# # #
# TX
tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
self.submodules += tx_fifo
self.comb += [
tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink),
# Generate TX IRQ when tx_fifo becomes non-full
self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
]
# RX
rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
self.submodules += rx_fifo
self.comb += [
Record.connect(phy.source, rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear),
# Generate RX IRQ when tx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.stb)
]示例11: __init__
def __init__(self):
self.sink = Sink(ULPI_DATA_D)
self.source = Source(ULPI_DATA_D)
self._ctl = CSRStorageEx(1)
snapshot = self._ctl.re
reset = self._ctl.storage[0]
self._num_ovf = Perfcounter(snapshot, reset)
self._num_total = Perfcounter(snapshot, reset)
self.comb += If(self.sink.stb, self._num_total.inc())
self.comb += If(self.source.stb &~ self.source.ack, self._num_ovf.inc())
valid = Signal()
data = Record(ULPI_DATA_D)
self.comb += [
If(self.sink.stb,
self.sink.ack.eq(1),
)]
self.sync += [
If(self.sink.stb,
valid.eq(1),
If(valid & ~self.source.ack,
data.rxcmd.eq(1),
data.d.eq(RXCMD_MAGIC_OVF),
).Else(
data.eq(self.sink.payload)
)
).Elif(self.source.ack,
valid.eq(0)
)]
self.comb += [
self.source.stb.eq(valid),
self.source.payload.eq(data)
]示例12: __init__
def __init__(self):
# in pix clock domain
self.valid_i = Signal()
self.vsync = Signal()
self.de = Signal()
self.r = Signal(8)
self.g = Signal(8)
self.b = Signal(8)
# in sys clock domain
self.frame = Source(frame_layout)
self.busy = Signal()
###
fifo_stb = Signal()
fifo_in = Record(frame_layout)
self.comb += [
fifo_stb.eq(self.valid_i & self.de),
fifo_in.r.eq(self.r),
fifo_in.g.eq(self.g),
fifo_in.b.eq(self.b),
]
vsync_r = Signal()
self.sync.pix += [
If(self.vsync & ~vsync_r, fifo_in.parity.eq(~fifo_in.parity)),
vsync_r.eq(self.vsync)
]
fifo = AsyncFIFO(layout_len(frame_layout), 256)
self.add_submodule(fifo, {"write": "pix", "read": "sys"})
self.comb += [
fifo.we.eq(fifo_stb),
fifo.din.eq(fifo_in.raw_bits()),
self.frame.stb.eq(fifo.readable),
self.frame.payload.raw_bits().eq(fifo.dout),
fifo.re.eq(self.frame.ack),
self.busy.eq(0)
]示例13: __init__
def __init__(self, phy,
tx_fifo_depth=16,
rx_fifo_depth=16):
self._rxtx = CSR(8)
self._txfull = CSRStatus()
self._rxempty = CSRStatus()
self.submodules.ev = EventManager()
self.ev.tx = EventSourceProcess()
self.ev.rx = EventSourceProcess()
self.ev.finalize()
# # #
tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth)
self.submodules += tx_fifo
self.comb += [
tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink)
]
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
self.submodules += rx_fifo
self.comb += [
Record.connect(phy.source, rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear)
]
self.comb += [
# Generate TX IRQ when tx_fifo becomes empty
self.ev.tx.trigger.eq(tx_fifo.source.stb),
# Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.stb),
]示例14: __init__
def __init__(self, pack_factor):
hbits_dyn = _hbits - log2_int(pack_factor)
timing_layout = [
("hres", hbits_dyn),
("hsync_start", hbits_dyn),
("hsync_end", hbits_dyn),
("hscan", hbits_dyn),
("vres", _vbits),
("vsync_start", _vbits),
("vsync_end", _vbits),
("vscan", _vbits)]
self.timing = Sink(timing_layout)
self.pixels = Sink(pixel_layout(pack_factor))
self.phy = Source(phy_layout(pack_factor))
self.busy = Signal()
###
hactive = Signal()
vactive = Signal()
active = Signal()
hcounter = Signal(hbits_dyn)
vcounter = Signal(_vbits)
skip = bpc - bpc_phy
self.comb += [
active.eq(hactive & vactive),
If(active,
[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
for p in ["p"+str(i) for i in range(pack_factor)] for c in ["y", "cb_cr"]],
self.phy.de.eq(1)
),
self.pixels.ack.eq(self.phy.ack & active)
]
load_timing = Signal()
tr = Record(timing_layout)
self.sync += If(load_timing, tr.eq(self.timing.payload))
generate_en = Signal()
generate_frame_done = Signal()
self.sync += [
generate_frame_done.eq(0),
If(generate_en,
hcounter.eq(hcounter + 1),
If(hcounter == 0, hactive.eq(1)),
If(hcounter == tr.hres, hactive.eq(0)),
If(hcounter == tr.hsync_start, self.phy.hsync.eq(1)),
If(hcounter == tr.hsync_end, self.phy.hsync.eq(0)),
If(hcounter == tr.hscan,
hcounter.eq(0),
If(vcounter == tr.vscan,
vcounter.eq(0),
generate_frame_done.eq(1)
).Else(
vcounter.eq(vcounter + 1)
)
),
If(vcounter == 0, vactive.eq(1)),
If(vcounter == tr.vres, vactive.eq(0)),
If(vcounter == tr.vsync_start, self.phy.vsync.eq(1)),
If(vcounter == tr.vsync_end, self.phy.vsync.eq(0))
)
]
self.submodules.fsm = FSM()
self.fsm.act("GET_TIMING",
self.timing.ack.eq(1),
load_timing.eq(1),
If(self.timing.stb, NextState("GENERATE"))
)
self.fsm.act("GENERATE",
self.busy.eq(1),
If(~active | self.pixels.stb,
self.phy.stb.eq(1),
If(self.phy.ack, generate_en.eq(1))
),
If(generate_frame_done, NextState("GET_TIMING"))
)示例15: __init__
def __init__(self):
super(Loopback, self).__init__()
self.comb += Record.connect(self.dout, self.din)