Python FSM.delayed_enter方法代码示例

# 需要导入模块: from migen.genlib.fsm import FSM [as 别名]
# 或者: from migen.genlib.fsm.FSM import delayed_enter [as 别名]
	def __init__(self, ulpi_reg):
		
		ReadAddress = Signal(6)
		
		write_fsm = FSM()
		self.submodules += write_fsm
		
		def delay_clocks(v, d):
			for i in range(d):
				n = Signal()
				self.sync += n.eq(v)
				v = n
			return v
		
		ulpi_reg_wack = delay_clocks(ulpi_reg.wack, 2)
		ulpi_reg_rack = delay_clocks(ulpi_reg.rack, 2)
		
		write_fsm.delayed_enter("RESET", "WRITE_HS_SNOOP", 16)

		write_fsm.act("WRITE_HS_SNOOP",
			ulpi_reg.waddr.eq(0x4),
			ulpi_reg.wdata.eq(0x48),
			ulpi_reg.wreq.eq(1),
			If(ulpi_reg_wack, NextState("WRITE_IDLE")))
		
		write_fsm.act("WRITE_IDLE",
			ulpi_reg.wreq.eq(0))
		
		read_fsm = FSM()
		self.submodules += read_fsm

		read_fsm.delayed_enter("RESET", "READ_REG", 16)
		
		read_fsm.act("READ_REG",
			ulpi_reg.raddr.eq(ReadAddress),
			ulpi_reg.rreq.eq(1),
			If(ulpi_reg_rack, NextState("READ_ACK")))
		
		self.sync += If(ulpi_reg_rack & ulpi_reg.rreq, ReadAddress.eq(ReadAddress + 1))
		
		read_fsm.act("READ_ACK",
			ulpi_reg.rreq.eq(0),
			If(~ulpi_reg_rack, NextState("READ_WAIT")))
		
		read_fsm.delayed_enter("READ_WAIT", "READ_REG", 16)

# 需要导入模块: from migen.genlib.fsm import FSM [as 别名]
# 或者: from migen.genlib.fsm.FSM import delayed_enter [as 别名]

#.........这里部分代码省略.........
		self.submodules += steerer
		
		# Read/write turnaround
		read_available = Signal()
		write_available = Signal()
		self.comb += [
			read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
			write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
		]
		
		def anti_starvation(timeout):
			en = Signal()
			max_time = Signal()
			if timeout:
				t = timeout - 1
				time = Signal(max=t+1)
				self.comb += max_time.eq(time == 0)
				self.sync += If(~en,
						time.eq(t)
					).Elif(~max_time,
						time.eq(time - 1)
					)
			else:
				self.comb += max_time.eq(0)
			return en, max_time
		read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
		write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
		
		# Refresh
		self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
		go_to_refresh = Signal()
		self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
		
		# Datapath
		all_rddata = [p.rddata for p in dfi.phases]
		all_wrdata = [p.wrdata for p in dfi.phases]
		all_wrdata_mask = [p.wrdata_mask for p in dfi.phases]
		self.comb += [
			lasmic.dat_r.eq(Cat(*all_rddata)),
			Cat(*all_wrdata).eq(lasmic.dat_w),
			Cat(*all_wrdata_mask).eq(~lasmic.dat_we)
		]
		
		# Control FSM
		fsm = FSM()
		self.submodules += fsm
		
		def steerer_sel(steerer, phy_settings, r_w_n):
			r = []
			for i in range(phy_settings.nphases):
				s = steerer.sel[i].eq(STEER_NOP)
				if r_w_n == "read":
					if i == phy_settings.rdphase:
						s = steerer.sel[i].eq(STEER_REQ)
					elif i == phy_settings.rdcmdphase:
						s = steerer.sel[i].eq(STEER_CMD)
				elif r_w_n == "write":
					if i == phy_settings.wrphase:
						s = steerer.sel[i].eq(STEER_REQ)
					elif i == phy_settings.wrcmdphase:
						s = steerer.sel[i].eq(STEER_CMD)
				else:
					raise ValueError
				r.append(s)
			return r

		fsm.act("READ",
			read_time_en.eq(1),
			choose_req.want_reads.eq(1),
			choose_cmd.cmd.ack.eq(1),
			choose_req.cmd.ack.eq(1),
			steerer_sel(steerer, phy_settings, "read"),
			If(write_available,
				# TODO: switch only after several cycles of ~read_available?
				If(~read_available | max_read_time, NextState("RTW"))
			),
			If(go_to_refresh, NextState("REFRESH"))
		)
		fsm.act("WRITE",
			write_time_en.eq(1),
			choose_req.want_writes.eq(1),
			choose_cmd.cmd.ack.eq(1),
			choose_req.cmd.ack.eq(1),
			steerer_sel(steerer, phy_settings, "write"),
			If(read_available,
				If(~write_available | max_write_time, NextState("WTR"))
			),
			If(go_to_refresh, NextState("REFRESH"))
		)
		fsm.act("REFRESH",
			steerer.sel[0].eq(STEER_REFRESH),
			If(~refresher.req, NextState("READ"))
		)
		fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
		fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
		fsm.finalize()
		self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])

		self.submodules.bandwidth = Bandwidth(choose_req.cmd)

# 需要导入模块: from migen.genlib.fsm import FSM [as 别名]
# 或者: from migen.genlib.fsm.FSM import delayed_enter [as 别名]

#.........这里部分代码省略.........

        # Request FIFO
        self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
        self.comb += [
            self.req_fifo.din.we.eq(req.we),
            self.req_fifo.din.adr.eq(req.adr),
            self.req_fifo.we.eq(req.stb),
            req.req_ack.eq(self.req_fifo.writable),
            self.req_fifo.re.eq(req.dat_ack),
            req.lock.eq(self.req_fifo.readable),
        ]
        reqf = self.req_fifo.dout

        slicer = _AddressSlicer(geom_settings.col_a, address_align)

        # Row tracking
        has_openrow = Signal()
        openrow = Signal(geom_settings.row_a)
        hit = Signal()
        self.comb += hit.eq(openrow == slicer.row(reqf.adr))
        track_open = Signal()
        track_close = Signal()
        self.sync += [
            If(track_open, has_openrow.eq(1), openrow.eq(slicer.row(reqf.adr))),
            If(track_close, has_openrow.eq(0)),
        ]

        # Address generation
        s_row_adr = Signal()
        self.comb += [
            self.cmd.ba.eq(bankn),
            If(s_row_adr, self.cmd.a.eq(slicer.row(reqf.adr))).Else(self.cmd.a.eq(slicer.col(reqf.adr))),
        ]

        # Respect write-to-precharge specification
        precharge_ok = Signal()
        t_unsafe_precharge = 2 + timing_settings.tWR - 1
        unsafe_precharge_count = Signal(max=t_unsafe_precharge + 1)
        self.comb += precharge_ok.eq(unsafe_precharge_count == 0)
        self.sync += [
            If(self.cmd.stb & self.cmd.ack & self.cmd.is_write, unsafe_precharge_count.eq(t_unsafe_precharge)).Elif(
                ~precharge_ok, unsafe_precharge_count.eq(unsafe_precharge_count - 1)
            )
        ]

        # Control and command generation FSM
        fsm = FSM()
        self.submodules += fsm
        fsm.act(
            "REGULAR",
            If(self.refresh_req, NextState("REFRESH")).Elif(
                self.req_fifo.readable,
                If(
                    has_openrow,
                    If(
                        hit,
                        # NB: write-to-read specification is enforced by multiplexer
                        self.cmd.stb.eq(1),
                        req.dat_ack.eq(self.cmd.ack),
                        self.cmd.is_read.eq(~reqf.we),
                        self.cmd.is_write.eq(reqf.we),
                        self.cmd.cas_n.eq(0),
                        self.cmd.we_n.eq(~reqf.we),
                    ).Else(NextState("PRECHARGE")),
                ).Else(NextState("ACTIVATE")),
            ),
        )
        fsm.act(
            "PRECHARGE",
            # Notes:
            # 1. we are presenting the column address, A10 is always low
            # 2. since we always go to the ACTIVATE state, we do not need
            # to assert track_close.
            If(
                precharge_ok,
                self.cmd.stb.eq(1),
                If(self.cmd.ack, NextState("TRP")),
                self.cmd.ras_n.eq(0),
                self.cmd.we_n.eq(0),
                self.cmd.is_cmd.eq(1),
            ),
        )
        fsm.act(
            "ACTIVATE",
            s_row_adr.eq(1),
            track_open.eq(1),
            self.cmd.stb.eq(1),
            self.cmd.is_cmd.eq(1),
            If(self.cmd.ack, NextState("TRCD")),
            self.cmd.ras_n.eq(0),
        )
        fsm.act(
            "REFRESH",
            self.refresh_gnt.eq(precharge_ok),
            track_close.eq(1),
            self.cmd.is_cmd.eq(1),
            If(~self.refresh_req, NextState("REGULAR")),
        )
        fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP - 1)
        fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD - 1)

# 需要导入模块: from migen.genlib.fsm import FSM [as 别名]
# 或者: from migen.genlib.fsm.FSM import delayed_enter [as 别名]

#.........这里部分代码省略.........
				)
			]

		self.sync += [
			If(refresh_ack,
				refresh_req.eq(0)
			),
			If(refresh_counter == 0,
				refresh_counter.eq(timing_settings.tREFI),
				refresh_req.eq(1)
			).Else(
				refresh_counter.eq(refresh_counter - 1)
			)
		]

		fsm = FSM()
		self.submodules += fsm
		fsm.act("IDLE",
			If(refresh_req,
				NextState("PRECHARGEALL")
			).Elif(bus.stb & bus.cyc,
				If(hit & bus.we,
					NextState("WRITE")
				),
				If(hit & ~bus.we,
					NextState("READ")
				),
				If(has_curbank_openrow & ~hit,
					NextState("PRECHARGE")
				),
				If(~has_curbank_openrow,
					NextState("ACTIVATE")
				),
			)
		)
		fsm.act("READ",
			# We output Column bits at address pins so A10 is 0
			# to disable row Auto-Precharge
			dfi.phases[rdphase].ras_n.eq(1),
			dfi.phases[rdphase].cas_n.eq(0),
			dfi.phases[rdphase].we_n.eq(1),
			dfi.phases[rdphase].rddata_en.eq(1),
			addr_sel.eq(COLUMN),
			NextState("READ-WAIT-ACK"),
		)
		fsm.act("READ-WAIT-ACK",
			If(dfi.phases[rdphase].rddata_valid,
				NextState("IDLE"),
				bus.ack.eq(1)
			).Else(
				NextState("READ-WAIT-ACK")
			)
		)
		fsm.act("WRITE",
			dfi.phases[wrphase].ras_n.eq(1),
			dfi.phases[wrphase].cas_n.eq(0),
			dfi.phases[wrphase].we_n.eq(0),
			dfi.phases[wrphase].wrdata_en.eq(1),
			addr_sel.eq(COLUMN),
			bus.ack.eq(1),
			NextState("IDLE")
		)
		fsm.act("PRECHARGEALL",
			row_closeall.eq(1),
			dfi.phases[rdphase].ras_n.eq(0),
			dfi.phases[rdphase].cas_n.eq(1),
			dfi.phases[rdphase].we_n.eq(0),
			addr_sel.eq(A10_ENABLED),
			NextState("PRE-REFRESH")
		)
		fsm.act("PRECHARGE",
			# Notes:
			# 1. we are presenting the column address so that A10 is low
			# 2. since we always go to the ACTIVATE state, we do not need
			# to assert row_close because it will be reopen right after.
			NextState("TRP"),
			addr_sel.eq(COLUMN),
			dfi.phases[rdphase].ras_n.eq(0),
			dfi.phases[rdphase].cas_n.eq(1),
			dfi.phases[rdphase].we_n.eq(0)
		)
		fsm.act("ACTIVATE",
			row_open.eq(1),
			NextState("TRCD"),
			dfi.phases[rdphase].ras_n.eq(0),
			dfi.phases[rdphase].cas_n.eq(1),
			dfi.phases[rdphase].we_n.eq(1),
			addr_sel.eq(ROW)
		)
		fsm.act("REFRESH",
			refresh_ack.eq(1),
			dfi.phases[rdphase].ras_n.eq(0),
			dfi.phases[rdphase].cas_n.eq(0),
			dfi.phases[rdphase].we_n.eq(1),
			NextState("POST-REFRESH")
		)
		fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
		fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1)
		fsm.delayed_enter("TRCD", "IDLE", timing_settings.tRCD-1)
		fsm.delayed_enter("POST-REFRESH", "IDLE", timing_settings.tRFC-1)

# 需要导入模块: from migen.genlib.fsm import FSM [as 别名]
# 或者: from migen.genlib.fsm.FSM import delayed_enter [as 别名]
	def __init__(self, cachesize, lasmim, wbm=None):
		if wbm is None:
			wbm = wishbone.Interface()
		self.wishbone = wbm

		###

		data_width = flen(self.wishbone.dat_r)
		if lasmim.dw < data_width:
			raise ValueError("LASMI data width must be >= {dw}".format(dw=data_width))
		if (lasmim.dw % data_width) != 0:
			raise ValueError("LASMI data width must be a multiple of {dw}".format(dw=data_width))

		# Split address:
		# TAG | LINE NUMBER | LINE OFFSET
		offsetbits = log2_int(lasmim.dw//data_width)
		addressbits = lasmim.aw + offsetbits
		linebits = log2_int(cachesize) - offsetbits
		tagbits = addressbits - linebits
		adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
		
		# Data memory
		data_mem = Memory(lasmim.dw, 2**linebits)
		data_port = data_mem.get_port(write_capable=True, we_granularity=8)
		self.specials += data_mem, data_port
		
		write_from_lasmi = Signal()
		write_to_lasmi = Signal()
		if adr_offset is None:
			adr_offset_r = None
		else:
			adr_offset_r = Signal(offsetbits)
			self.sync += adr_offset_r.eq(adr_offset)

		self.comb += [
			data_port.adr.eq(adr_line),
			If(write_from_lasmi,
				data_port.dat_w.eq(lasmim.dat_r),
				data_port.we.eq(Replicate(1, lasmim.dw//8))
			).Else(
				data_port.dat_w.eq(Replicate(self.wishbone.dat_w, lasmim.dw//data_width)),
				If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
					displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
				)
			),
			If(write_to_lasmi, 
				lasmim.dat_w.eq(data_port.dat_r),
				lasmim.dat_we.eq(2**(lasmim.dw//8)-1)
			),
			chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
		]

		
		# Tag memory
		tag_layout = [("tag", tagbits), ("dirty", 1)]
		tag_mem = Memory(layout_len(tag_layout), 2**linebits)
		tag_port = tag_mem.get_port(write_capable=True)
		self.specials += tag_mem, tag_port
		tag_do = Record(tag_layout)
		tag_di = Record(tag_layout)
		self.comb += [
			tag_do.raw_bits().eq(tag_port.dat_r),
			tag_port.dat_w.eq(tag_di.raw_bits())
		]
			
		self.comb += [
			tag_port.adr.eq(adr_line),
			tag_di.tag.eq(adr_tag),
			lasmim.adr.eq(Cat(adr_line, tag_do.tag))
		]
		
		# Control FSM
		assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1)
		fsm = FSM()
		self.submodules += fsm
		
		fsm.delayed_enter("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1)
		fsm.delayed_enter("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1)

		fsm.act("IDLE",
			If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
		)
		fsm.act("TEST_HIT",
			If(tag_do.tag == adr_tag,
				self.wishbone.ack.eq(1),
				If(self.wishbone.we,
					tag_di.dirty.eq(1),
					tag_port.we.eq(1)
				),
				NextState("IDLE")
			).Else(
				If(tag_do.dirty,
					NextState("EVICT_REQUEST")
				).Else(
					NextState("REFILL_WRTAG")
				)
			)
		)
		
		fsm.act("EVICT_REQUEST",
#.........这里部分代码省略.........