Python tools.write_to_file函数代码示例

    def _build_batch(self, platform, sources, build_name):
        tcl = []
        for filename, language, library in sources:
            tcl.append("add_files " + filename)
            tcl.append("set_property library {} [get_files {}]".format(library, filename))

        tcl.append("read_xdc {}.xdc".format(build_name))
        tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
        tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
        tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
        tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
        tcl.append("place_design")
        if self.with_phys_opt:
            tcl.append("phys_opt_design -directive AddRetime")
        tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
        tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
        tcl.append("report_io -file {}_io.rpt".format(build_name))
        tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
        tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
        tcl.append("route_design")
        tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
        tcl.append("report_drc -file {}_drc.rpt".format(build_name))
        tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name))
        tcl.append("report_power -file {}_power.rpt".format(build_name))
        for bitstream_command in self.bitstream_commands:
            tcl.append(bitstream_command.format(build_name=build_name))
        tcl.append("write_bitstream -force {}.bit ".format(build_name))
        for additional_command in self.additional_commands:
            tcl.append(additional_command.format(build_name=build_name))
        tcl.append("quit")
        tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def _run_ise(build_name, ise_path, source):
    if sys.platform == "win32" or sys.platform == "cygwin":
        source = False
    build_script_contents = "# Autogenerated by mibuild\nset -e\n"
    if source:
        vers = [ver for ver in os.listdir(ise_path) if _is_valid_version(ise_path, ver)]
        tools_version = max(vers)
        bits = struct.calcsize("P") * 8
        xilinx_settings_file = "%s/%s/ISE_DS/settings%d.sh" % (ise_path, tools_version, bits)
        build_script_contents += "source " + xilinx_settings_file + "\n"

    build_script_contents += """
xst -ifn {build_name}.xst
ngdbuild -uc {build_name}.ucf {build_name}.ngc
map -ol high -w {build_name}.ngd
par -ol high -w {build_name}.ncd {build_name}-routed.ncd
bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit
""".format(
        build_name=build_name
    )
    build_script_file = "build_" + build_name + ".sh"
    tools.write_to_file(build_script_file, build_script_contents)

    r = subprocess.call(["bash", build_script_file])
    if r != 0:
        raise OSError("Subprocess failed")

def _build_files(device, sources, vincpaths, build_name, bitstream_compression):
	tcl = []
	for filename, language in sources:
		tcl.append("add_files " + filename.replace("\\", "/"))

	tcl.append("read_xdc %s.xdc" %build_name)
	tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(device, " ".join(vincpaths)))
	tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
	tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
	tcl.append("place_design")
	tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name))
	tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
	tcl.append("report_io -file %s_io.rpt" %(build_name))
	tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
	tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
	tcl.append("route_design")
	tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
	tcl.append("report_drc -file %s_drc.rpt" %(build_name))
	tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
	tcl.append("report_power -file %s_power.rpt" %(build_name))
	if bitstream_compression:
		tcl.append("set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
	tcl.append("write_bitstream -force %s.bit " %build_name)
	tcl.append("quit")
	tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
        bitgen_opt, ise_commands, map_opt, par_opt, ver=None):
    if sys.platform == "win32" or sys.platform == "cygwin":
        source = False
    build_script_contents = "# Autogenerated by mibuild\nset -e\n"
    if source:
        settings = common.settings(ise_path, ver, "ISE_DS")
        build_script_contents += "source " + settings + "\n"
    if mode == "edif":
        ext = "edif"
    else:
        ext = "ngc"
        build_script_contents += """
xst -ifn {build_name}.xst
"""

    build_script_contents += """
ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd
map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
"""
    build_script_contents = build_script_contents.format(build_name=build_name,
            ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext,
            par_opt=par_opt, map_opt=map_opt)
    build_script_contents += ise_commands.format(build_name=build_name)
    build_script_file = "build_" + build_name + ".sh"
    tools.write_to_file(build_script_file, build_script_contents, force_unix=True)

    r = subprocess.call(["bash", build_script_file])
    if r != 0:
        raise OSError("Subprocess failed")

def _run_yosys(device, sources, vincpaths, build_name):
	ys_contents = ""
	incflags = ""
	for path in vincpaths:
		incflags += " -I" + path
	for filename, language in sources:
		ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
	
	if device[:2] == "xc":
		archcode = device[2:4]
	else:
		archcode = device[0:2]
	arch = {
		"6s": "spartan6",
		"7a": "artix7",
		"7k": "kintex7",
		"7v": "virtex7",
		"7z": "zynq7000"
	}[archcode]
	
	ys_contents += """hierarchy -check -top top
proc; memory; opt; fsm; opt
synth_xilinx -arch {arch} -top top -edif {build_name}.edif""".format(arch=arch, build_name=build_name)
	
	ys_name = build_name + ".ys"
	tools.write_to_file(ys_name, ys_contents)
	r = subprocess.call(["yosys", ys_name])
	if r != 0:
		raise OSError("Subprocess failed")

def _run_sim(build_name):
    run_script_contents = """obj_dir/Vdut
"""
    run_script_file = "run_" + build_name + ".sh"
    tools.write_to_file(run_script_file, run_script_contents, force_unix=True)
    r = subprocess.call(["bash", run_script_file])
    if r != 0:
        raise OSError("Subprocess failed")

def _build_files(device, sources, named_sc, named_pc, build_name):
	qsf_contents = ""
	for filename, language in sources:
		qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"

	qsf_contents += _build_qsf(named_sc, named_pc)
	qsf_contents += "set_global_assignment -name DEVICE " + device
	tools.write_to_file(build_name + ".qsf", qsf_contents)

def main():
	platform = m1.Platform()
	soc = top.SoC(platform)
	
	platform.add_platform_command("""
NET "{clk50}" TNM_NET = "GRPclk50";
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
""", clk50=platform.lookup_request("clk50"))

	platform.add_platform_command("""
INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";

PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")

	if hasattr(soc, "fb"):
		platform.add_platform_command("""
NET "vga_clk" TNM_NET = "GRPvga_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
""")

	if hasattr(soc, "minimac"):
		platform.add_platform_command("""
NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
""",
		phy_rx_clk=platform.lookup_request("eth_clocks").rx,
		phy_tx_clk=platform.lookup_request("eth_clocks").tx,)

	if hasattr(soc, "dvisampler0"):
		platform.add_platform_command("""
NET "{dviclk0}" TNM_NET = "GRPdviclk0";
NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
""", dviclk0=platform.lookup_request("dvi_in", 0).clk)
	if hasattr(soc, "dvisampler1"):
		platform.add_platform_command("""
NET "{dviclk1}" TNM_NET = "GRPdviclk1";
NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
""", dviclk1=platform.lookup_request("dvi_in", 1).clk)
	mor1kx_dir = os.path.join("mor1kx", "submodule", "rtl", "verilog")
	for d in ["m1crg", "s6ddrphy", "minimac3", mor1kx_dir]:
		platform.add_source_dir(os.path.join("verilog", d))

	platform.build_cmdline(soc)
	csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
	write_to_file("software/include/hw/csr.h", csr_header)

 def export(self, vns, filename):
     def format_line(*args):
         return ",".join(args) + "\n"
     r = ""
     r += format_line("config", "dw", str(self.dw))
     r += format_line("config", "depth", str(self.depth))
     r += format_line("config", "with_rle", str(int(self.with_rle)))
     if not isinstance(self.layout, tuple):
         self.layout = [self.layout]
     for e in self.layout:
         r += format_line("layout", vns.get_name(e), str(flen(e)))
     write_to_file(filename, r)

def _build_files(device, sources, vincpaths, build_name):
    tcl = []
    tcl.append("prj_project new -name \"{}\" -impl \"implementation\" -dev {} -synthesis \"synplify\"".format(build_name, device))
    for path in vincpaths:
        tcl.append("prj_impl option {include path} {\"" + path + "\"}")
    for filename, language, library in sources:
        tcl.append("prj_src add \"" + filename + "\" -work " + library)
    tcl.append("prj_run Synthesis -impl implementation -forceOne")
    tcl.append("prj_run Translate -impl implementation")
    tcl.append("prj_run Map -impl implementation")
    tcl.append("prj_run PAR -impl implementation")
    tcl.append("prj_run Export -impl implementation -task Bitgen")
    tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def _run_diamond(build_name, source, ver=None):
    if sys.platform == "win32" or sys.platform == "cygwin":
        build_script_contents = "REM Autogenerated by mibuild\n"
        build_script_contents = "pnmainc " + build_name + ".tcl\n"
        build_script_file = "build_" + build_name + ".bat"
        tools.write_to_file(build_script_file, build_script_contents)
        r = subprocess.call([build_script_file])
        shutil.copy(os.path.join("implementation", build_name + "_implementation.bit"), build_name + ".bit")
    else:
        raise NotImplementedError

    if r != 0:
        raise OSError("Subprocess failed")

    def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", source=True, run=True):
        tools.mkdir_noerror(build_dir)
        os.chdir(build_dir)

        v_src, named_sc, named_pc = self.get_verilog(fragment)
        v_file = build_name + ".v"
        tools.write_to_file(v_file, v_src)
        sources = self.sources + [(v_file, "verilog")]
        _build_files(self.device, sources, named_sc, named_pc, build_name)
        if run:
            _run_ise(build_name, ise_path, source)

        os.chdir("..")

def main():
	args = _get_args()

	platform_module = _misoc_import("mibuild.platforms", args.external_platform, args.platform)
	target_module = _misoc_import("targets", args.external_target, args.target)
	platform = platform_module.Platform()
	if args.sub_target:
		top_class = getattr(target_module, args.sub_target)
	else:
		top_class = target_module.get_default_subtarget(platform)
	build_name = top_class.__name__.lower() + "-" + args.platform
	top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
	soc = top_class(platform, **top_kwargs)

	soc.finalize()

	if not args.no_header:
		boilerplate = """/*
 * Platform: {}
 * Target: {}
 * Subtarget: {}
 */

""".format(args.platform, args.target, top_class.__name__)
		linker_header = cpuif.get_linker_regions(soc.cpu_memory_regions)
		write_to_file("software/include/generated/regions.ld", boilerplate + linker_header)
		csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
		write_to_file("software/include/generated/csr.h", boilerplate + csr_header)
		if hasattr(soc, "ddrphy"):
			sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
			write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header)
	if args.csr_csv:
		csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
		write_to_file(args.csr_csv, csr_csv)

	if hasattr(soc, "init_bios_memory"):
		ret = subprocess.call(["make", "-C", "software/bios"])
		if ret:
			raise OSError("BIOS build failed")
		bios_file = open("software/bios/bios.bin", "rb")
		bios_data = []
		while True:
			w = bios_file.read(4)
			if not w:
				break
			bios_data.append(struct.unpack(">I", w)[0])
		bios_file.close()
		soc.init_bios_memory(bios_data)

	if not args.no_bitstream:
		build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
		platform.build(soc, build_name=build_name, **build_kwargs)
		subprocess.call(["tools/byteswap",
			"build/" + build_name + ".bin",
			"build/" + build_name + ".fpg"])

	if args.load:
		jtag.load(platform.name, "build/" + build_name + ".bit")
	if args.flash:
		jtag.flash("build/" + build_name + ".fpg")

def _build_files(device, sources, vincpaths, build_name):
	tcl_contents = ""
	for filename, language in sources:
		tcl_contents += "add_files " + filename.replace("\\", "/") + "\n"

	tcl_contents += "read_xdc %s.xdc\n" %build_name
	tcl_contents += "synth_design -top top -part %s -include_dirs {%s}\n" %(device, " ".join(vincpaths))
	tcl_contents += "place_design\n"
	tcl_contents += "route_design\n"
	tcl_contents += "report_timing_summary -file %s_timing.rpt\n" %(build_name)
	tcl_contents += "report_utilization -file %s_utilization.rpt\n" %(build_name)
	tcl_contents += "write_bitstream -force %s.bit \n" %build_name
	tcl_contents += "quit\n"	
	tools.write_to_file(build_name + ".tcl", tcl_contents)

def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
	qsf_contents = ""
	for filename, language in sources:
		# Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
		if language == "verilog":
			language = "systemverilog"
		qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"

	for path in vincpaths:
		qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\","/") + "\n"

	qsf_contents += _build_qsf(named_sc, named_pc)
	qsf_contents += "set_global_assignment -name DEVICE " + device
	tools.write_to_file(build_name + ".qsf", qsf_contents)