Python Crc.gen_table方法代码示例

# 需要导入模块: from crc_algorithms import Crc [as 别名]
# 或者: from crc_algorithms.Crc import gen_table [as 别名]
 def __get_table_init(self):
     """
     Return the precalculated CRC table for the table_driven implementation.
     """
     if self.opt.Algorithm != self.opt.Algo_Table_Driven:
         return "0"
     if self.opt.Width == None or self.opt.Poly == None or self.opt.ReflectIn == None:
         return "0"
     crc = Crc(width = self.opt.Width, poly = self.opt.Poly,
             reflect_in = self.opt.ReflectIn,
             xor_in = 0, reflect_out = False, xor_out = 0,       # set unimportant variables to known values
             table_idx_width = self.opt.TableIdxWidth)
     tbl = crc.gen_table()
     if self.opt.Width >= 32:
         values_per_line = 4
     elif self.opt.Width >= 16:
         values_per_line = 8
     else:
         values_per_line = 16
     format_width = max(self.opt.Width, 8)
     out  = ""
     for i in range(self.opt.TableWidth):
         if i % values_per_line == 0:
             out += "    "
         if i == (self.opt.TableWidth - 1):
             out += "%s" % self.__pretty_hex(tbl[i], format_width)
         elif i % values_per_line == (values_per_line - 1):
             out += "%s,\n" % self.__pretty_hex(tbl[i], format_width)
         else:
             out += "%s, " % self.__pretty_hex(tbl[i], format_width)
     return out

# 需要导入模块: from crc_algorithms import Crc [as 别名]
# 或者: from crc_algorithms.Crc import gen_table [as 别名]
 def __get_crc_bwe_bitmask_minterms(self):
     """
     Return a list of (bitmask, minterms), for all bits.
     """
     crc = Crc(width = self.opt.Width, poly = self.opt.Poly,
             reflect_in = self.opt.ReflectIn, xor_in = self.opt.XorIn,
             reflect_out = self.opt.ReflectOut, xor_out = self.opt.XorOut,
             table_idx_width = self.opt.TableIdxWidth)
     qm = QuineMcCluskey(use_xor = True)
     crc_tbl = crc.gen_table()
     bm_mt = []
     for bit in range(max(self.opt.Width, 8)):
         ones = [i for i in range(self.opt.TableWidth) if crc_tbl[i] & (1 << bit) != 0]
         terms = qm.simplify(ones, [])
         if self.opt.Verbose:
             print("bit %02d: %s" % (bit, terms))
         if terms != None:
             for term in terms:
                 shifted_term = '.' * bit + term + '.' * (self.opt.Width - bit - 1)
                 bm_mt.append((1 << bit, shifted_term))
     return bm_mt

# 需要导入模块: from crc_algorithms import Crc [as 别名]
# 或者: from crc_algorithms.Crc import gen_table [as 别名]
	def parse(self):
		data = None
		self.title = '[empty]'
		for idx,s in enumerate(self.sig):
			if s[0:6] == "TITLE:":
				self.title = s[6:].replace(':', ';')
				continue
			if s[0:5] == "TYPE:":
				self.typeDesc = TypeDesc(s[5:])
				continue
			if s[0:5] == "DATA:":
				data = self.sig[idx+1:]
				continue
		if not data:
			raise DataException('error in data of signature at line ' + str(self.sigLineNumber) + ' named: ' + self.title)
		try:
			self.data = DataParser(self.typeDesc, data)
		except DataException as de:
			raise DataException('error in data of signature at line ' + str(self.sigLineNumber) + ' named: ' + self.title + ' child info:' + de.value)

		#debugRewrite("TITLE:"+self.title.replace(';',':')+"\n\n")
		#debugRewrite("TYPE:"+str(self.typeDesc)+"\n")
		#debugRewrite("DATA:\n");
		#debugRewrite(str(self.data));
		#debugRewrite("\n----\n\n")

		if self.typeDesc.isSimple():
			for bitWidth in self.typeDesc.values:
				# lil endian
				b,l = self.dumpData(bitWidth, Little_Endian, self.data)
				self.generateSigName(self.ndb, bitWidth, Little_Endian, b, l)

				if bitWidth == 8:
					continue

				# big endian
				b,l = self.dumpData(bitWidth, Big_Endian, self.data)
				self.generateSigName(self.ndb, bitWidth, Big_Endian, b, l)

		# currently if "CRC:" is specified only one width is allowed
		elif self.typeDesc.isCrc:
			for Do_Reflect in [True, False]:
				bitWidth = self.typeDesc.values.keys()[0]
				crc = Crc(width = bitWidth, poly = self.data.values[0], reflect_in = Do_Reflect, xor_in = 0, reflect_out = Do_Reflect, xor_out = 0)
				dummyData = DummyData(crc.gen_table(), False)

				b,l = self.dumpData(bitWidth, Little_Endian, dummyData)
				self.generateCrcSigName(bitWidth, Little_Endian, Do_Reflect, b)
				if bitWidth != 8:
					b,l = self.dumpData(bitWidth, Big_Endian, dummyData)
					self.generateCrcSigName(bitWidth, Big_Endian, Do_Reflect, b)

		elif self.typeDesc.isLog:
			for bitWidth in self.typeDesc.values:
				if bitWidth == 8:
					print "\n [!] WARNING, generated byte-based logical signatures is a bad, BAD idea\n"
				b = self.dumpLogicalSignature(bitWidth, Little_Endian, self.data)
				self.generateSigName(self.ldb, bitWidth, Little_Endian, b, 0)

				if bitWidth != 8:
					b = self.dumpLogicalSignature(bitWidth, Big_Endian, self.data)
					self.generateSigName(self.ldb, bitWidth, Big_Endian, b, 0)