本文整理汇总了Python中control.Control.getBtaken方法的典型用法代码示例。如果您正苦于以下问题：Python Control.getBtaken方法的具体用法？Python Control.getBtaken怎么用？Python Control.getBtaken使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类control.Control的用法示例。
在下文中一共展示了Control.getBtaken方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: Pipelinecpu
# 需要导入模块: from control import Control [as 别名]
# 或者: from control.Control import getBtaken [as 别名]
class Pipelinecpu(object):
'''This class is the pipelinecpu'''
def __init__(self):
self.control = Control()
self.register = Registers(32)
self.pcreg = PipelineReg()
self.if_id = PipelineReg()
self.id_exe = PipelineReg()
self.exe_mem = PipelineReg()
self.mem_wb = PipelineReg()
self.alu = Alu()
self.memory = Memory()
self.initializePipeline()
def getRegisterState(self):
return self.register.getRegisterState()
def getInstructionCount(self):
return self.instructionCount
def getDataCount(self):
return self.dataCount
def getInstruction(self, i):
return self.memory.readMemory(i)
def readMemory(self, i):
return self.memory.readMemory(i)
def getPC(self):
return self.pc
def initializePipeline(self):
## Deletes memory and instruction count
self.signalWPC = 1
self.signalWIR = 1
self.regData = 0
self.pc = 0
self.signalBtaken = 0
self.signalSld = 0
self.signalWreg = 0
self.signalLOADDEPEN = 1
self.inst = ''
self.signalShift = 0
self.tempinst = ''
## Initializes Registers
self.memory.initialize()
self.register.initialize()
self.pcreg.initialize()
self.if_id.initialize()
self.id_exe.initialize()
self.exe_mem.initialize()
self.mem_wb.initialize()
## Forwarding Unit
def __forwardingUnit(self):
int2 = functools.partial(int, base=2)
self.rs1IsReg = (self.opcode != int2(opcodes['bne'])) & (self.opcode != int2(opcodes['beq'])) & (
self.opcode != int2(opcodes['branch']))
self.rs2IsReg = (self.opcode == int2(opcodes['and'])) | (self.opcode == int2(opcodes['or'])) | (
self.opcode == int2(opcodes['add'])) | \
(self.opcode == int2(opcodes['sub'])) | (self.opcode == int2(opcodes['sra'])) | (
self.opcode == int2(opcodes['sll'])) | \
(self.opcode == int2(opcodes['srl']))
# ALU A select signal
ADEPEN1 = ((self.exe_mem.signalWreg == 1) & (self.readReg1 == self.exe_mem.regD) | (self.mem_wb.signalWreg == 1) & \
(self.readReg1 == self.mem_wb.regD)) & (self.rs1IsReg)
ADEPEN2 = ((self.mem_wb.signalWreg == 1) & (self.readReg1 == self.mem_wb.regD)) & (self.rs1IsReg)
self.signalADEPEN = ADEPEN1 * 2 + ADEPEN2
#ALU B select signal
BDEPEN1 = ((self.exe_mem.signalWreg == 1) & (self.readReg2 == self.exe_mem.regD) | (self.mem_wb.signalWreg == 1) & \
(self.readReg2 == self.mem_wb.regD)) & (self.rs2IsReg)
BDEPEN2 = (self.mem_wb.signalWreg == 1) & (self.readReg2 == self.mem_wb.regD) & (self.rs2IsReg) | (
not self.rs2IsReg)
self.signalBDEPEN = BDEPEN1 * 2 + BDEPEN2
#LOADDEPEN
EXE_A_DEPEN = (self.readReg1 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.rs1IsReg)
EXE_B_DEPEN = (self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.rs2IsReg) | \
(self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.opcode == int2(opcodes['store']))
self.signalLOADDEPEN = not (EXE_A_DEPEN | EXE_B_DEPEN)
#STORE
self.signalQDEPEN = (self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalWreg == 1)
## Instruction Fetch Stage
def __cpuStageIF(self, bin_instruction, instruction):
self.signalBtaken = self.control.getBtaken()
if self.signalBtaken:
self.nextPC = twos_to_int(self.if_id.instruction & 0x3FFFFFF, 26)
else:
self.nextPC = self.pc + 1
int2 = functools.partial(int, base=2)
if self.opcode == 10 or self.opcode == 11:
self.signalWPC = not(((self.opcode == int2(opcodes['bne'])) | (self.opcode == int2(opcodes['beq']))) & \
self.exe_mem.signalWreg & (not self.exe_mem.signalSld))
#.........这里部分代码省略.........