本文整理汇总了Python中chipwhisperer.common.utils.parameter.Parameter.refreshAllParameters方法的典型用法代码示例。如果您正苦于以下问题：Python Parameter.refreshAllParameters方法的具体用法？Python Parameter.refreshAllParameters怎么用？Python Parameter.refreshAllParameters使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类chipwhisperer.common.utils.parameter.Parameter的用法示例。
在下文中一共展示了Parameter.refreshAllParameters方法的2个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的Python代码示例。
示例1: ClockSettings
# 需要导入模块: from chipwhisperer.common.utils.parameter import Parameter [as 别名]
# 或者: from chipwhisperer.common.utils.parameter.Parameter import refreshAllParameters [as 别名]
class ClockSettings(Parameterized):
_name = 'Clock Setup'
readMask = [0x1f, 0xff, 0xff, 0xfd]
def __init__(self, oaiface, hwinfo=None):
self.oa = oaiface
self._hwinfo = hwinfo
self.params = Parameter(name=self.getName(), type='group')
self.params.addChildren([
{'name':'Refresh Status', 'type':'action', 'linked':[('ADC Clock', 'DCM Locked'), ('ADC Clock', 'ADC Freq'), ('CLKGEN Settings', 'DCM Locked'), 'Freq Counter'],
'help':'%namehdr%' +
'Update if the Digital Clock Manager (DCM) are "locked" and their operating frequency.'},
{'name':'Reset DCMs', 'type':'action', 'action':self.resetDcms, 'linked':[('CLKGEN Settings', 'Multiply'), ('CLKGEN Settings', 'Divide')],
'help':'%namehdr%' +
'When the input frequency to the DCM blocks changes, it can cause them to become "unlocked". When they are "unlocked" they are NOT ' +
'generating a reliable output frequency. You must press the "Reset" button to cause them to re-lock. This is currently not automatically ' +
'done as during regular operation they shouldn\'t become unlocked.\n\nHowever every time you change the DCM block source, it will cause ' +
'the blocks to lose lock.'},
{'name': 'ADC Clock', 'type':'group', 'children': [
{'name': 'Source', 'type':'list', 'values':{"EXTCLK Direct":("extclk", 4, "clkgen"),
"EXTCLK x4 via DCM":("dcm", 4, "extclk"),
"EXTCLK x1 via DCM":("dcm", 1, "extclk"),
"CLKGEN x4 via DCM":("dcm", 4, "clkgen"),
"CLKGEN x1 via DCM":("dcm", 1, "clkgen")},
'set':self.setAdcSource, 'get':self.adcSource,
'help':'%namehdr%' +
'The ADC sample clock is generated from this source. Options are either an external input (which input set elsewhere) or an internal clock generator. Details of each option:\n\n' +
'=================== ====================== =================== ===============\n' +
' Name Description Input Freq Range Fine Phase Adj.\n' +
'=================== ====================== =================== ===============\n' +
' EXCLK Direct Connects sample clock 1-105 MHz NO\n' +
' external pin directly.\n' +
' EXTCLK xN via DCM Takes external pin, 5-105 MHz (x1) YES\n\n' +
' multiplies frequency 5-26.25 MHz (x4) \n\n' +
' xN and feeds to ADC. \n' +
' CLKGEN xN via DCM Multiples CLKGEN by 5-105 MHz (x1) YES\n\n' +
' xN and feeds to ADC. 5-26.25 MHz (x4) \n\n' +
'=================== ====================== =================== ===============\n'},
{'name': 'Phase Adjust', 'type':'int', 'limits':(-255, 255), 'set':self.setPhase, 'get':self.phase, 'help':'%namehdr%' +
'Makes small amount of adjustment to sampling point compared to the clock source. This can be used to improve the stability ' +
'of the measurement. Total phase adjustment range is < 5nS regardless of input frequency.'},
{'name': 'ADC Freq', 'type': 'int', 'siPrefix':True, 'suffix': 'Hz', 'readonly':True, 'get':self.adcFrequency},
{'name': 'DCM Locked', 'type':'bool', 'get':self.dcmADCLocked, 'readonly':True},
{'name':'Reset ADC DCM', 'type':'action', 'action':lambda _ : self.resetDcms(True, False), 'linked':['Phase Adjust']},
]},
{'name': 'Freq Counter', 'type': 'str', 'readonly':True, 'get':lambda: str(self.extFrequency()) + " Hz"},
{'name': 'Freq Counter Src', 'type':'list', 'values':{'EXTCLK Input':0, 'CLKGEN Output':1}, 'set':self.setFreqSrc, 'get':self.freqSrc},
{'name': 'CLKGEN Settings', 'type':'group', 'children': [
{'name':'Input Source', 'type':'list', 'values':["system", "extclk"], 'set':self.setClkgenSrc, 'get':self.clkgenSrc},
{'name':'Multiply', 'type':'int', 'limits':(2, 256), "default":2, 'set':self.setClkgenMul, 'get':self.clkgenMul, 'linked':['Current Frequency']},
{'name':'Divide', 'type':'int', 'limits':(1, 256), 'set':self.setClkgenDiv, 'get':self.clkgenDiv, 'linked':['Current Frequency']},
{'name':'Desired Frequency', 'type':'float', 'limits':(3.3E6, 200E6), 'default':0, 'step':1E6, 'siPrefix':True, 'suffix':'Hz',
'set':self.autoMulDiv, 'get':self.getClkgen, 'linked':['Multiply', 'Divide']},
{'name':'Current Frequency', 'type':'str', 'default':0, 'readonly':True,
'get':lambda: str(self.getClkgen()) + " Hz"},
{'name':'DCM Locked', 'type':'bool', 'default':False, 'get':self.clkgenLocked, 'readonly':True},
{'name':'Reset CLKGEN DCM', 'type':'action', 'action':lambda _ : self.resetDcms(False, True), 'linked':['Multiply', 'Divide']},
]}
])
self.params.refreshAllParameters()
@setupSetParam("Freq Counter Src")
def setFreqSrc(self, src):
result = self.oa.sendMessage(CODE_READ, ADDR_ADVCLK, maxResp=4)
result[3] = result[3] & ~(0x08)
result[3] |= src << 3
#print "%x"%result[3]
self.oa.sendMessage(CODE_WRITE, ADDR_ADVCLK, result, readMask=self.readMask)
def freqSrc(self):
if self.oa is None:
return 0
result = self.oa.sendMessage(CODE_READ, ADDR_ADVCLK, maxResp=4)
return ((result[3] & 0x08) >> 3)
def getClkgen(self):
return (self._hwinfo.sysFrequency() * self.clkgenMul()) / self.clkgenDiv()
@setupSetParam(['CLKGEN Settings', 'Desired Frequency'])
def autoMulDiv(self, freq):
inpfreq = self._hwinfo.sysFrequency()
sets = self.calculateClkGenMulDiv(freq, inpfreq)
self.setClkgenMul(sets[0])
self.setClkgenDiv(sets[1])
self.resetDcms(False, True)
def calculateClkGenMulDiv(self, freq, inpfreq=30E6):
"""Calculate Multiply & Divide settings based on input frequency"""
#Max setting for divide is 60 (see datasheet)
#Multiply is 2-256
lowerror = 1E99
best = (0, 0)
# From datasheet, if input freq is < 52MHz limit max divide
if inpfreq < 52E6:
maxdiv = int(inpfreq / 0.5E6)
else:
#.........这里部分代码省略.........
示例2: ChipWhispererGlitch
# 需要导入模块: from chipwhisperer.common.utils.parameter import Parameter [as 别名]
# 或者: from chipwhisperer.common.utils.parameter.Parameter import refreshAllParameters [as 别名]
#.........这里部分代码省略.........
self.prEnabled = False
except OSError as e: # Also catches WindowsError
logging.error(str(e))
self.prEnabled = False
if self.prEnabled:
# Enable glitch width, check what we've got access to
self.findParam('width').setReadonly(False)
lim = (self.glitchPR.limitList[0][0] / 2.55, self.glitchPR.limitList[0][1] / 2.55)
self.findParam('width').setLimits(lim)
self.findParam('offset').setReadonly(False)
lim = (self.glitchPR.limitList[1][0] / 2.55, self.glitchPR.limitList[1][1] / 2.55)
self.findParam('offset').setLimits(lim)
self.setOpenADC(oa)
def setOpenADC(self, oa):
self.oa = None
if self.prEnabled:
self.prCon.con(oa)
# Check this is actually working
if self.prCon.isPresent() == False:
self.prEnabled = False
logging.warning('Partial Reconfiguration block not detected, PR disabled')
return
# Reset FPGA back to defaults in case previous bitstreams loaded
self.updatePartialReconfig()
self.oa = oa
try:
self.params.refreshAllParameters()
except TypeError:
return
def updatePartialReconfig(self, _=None):
"""
Reads the values set via the GUI & updates the hardware settings for partial reconfiguration. Checks that PR
is enabled with self.prEnabled.
"""
width = float(self.findParam('width').getValue())
offset = float(self.findParam('offset').getValue())
widthint = round((width / 100) * 256)
offsetint = round((offset / 100) * 256)
if widthint == 0:
logging.warning('Partial reconfiguration for width = 0 may not work')
if offsetint == 0:
logging.warning('Partial reconfiguration for width = 0 may not work')
bs = self.glitchPR.getPartialBitstream([widthint, offsetint])
if self.prEnabled:
self.prCon.program(bs)
if self.oa is not None:
self.resetDCMs(keepPhase=True)
# print "Partial: %d %d" % (widthint, offsetint)
self.updateGlitchReadBack()
def updateGlitchReadBack(self, test=False):