本文整理汇总了C#中ListItem.isAllZeros方法的典型用法代码示例。如果您正苦于以下问题：C# ListItem.isAllZeros方法的具体用法？C# ListItem.isAllZeros怎么用？C# ListItem.isAllZeros使用的例子？那么恭喜您, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类ListItem的用法示例。
在下文中一共展示了ListItem.isAllZeros方法的2个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C#代码示例。
示例1: createByteArray
public static byte[] createByteArray(TimestepTimebaseSegmentCollection segments,
SequenceData sequence, out int nSegments, double masterClockPeriod, bool assymetric)
{
List<ListItem> listItems = new List<ListItem>();
for (int stepID = 0; stepID < sequence.TimeSteps.Count; stepID++)
{
if (sequence.TimeSteps[stepID].StepEnabled)
{
if (sequence.TimeSteps[stepID].WaitForRetrigger)
{
listItems.Add(new ListItem(0, 0, 0)); // 0,0,0 list item is code for "wait for retrigger
// FPGA knows how to handle this
}
List<SequenceData.VariableTimebaseSegment> stepSegments = segments[sequence.TimeSteps[stepID]];
for (int i = 0; i < stepSegments.Count; i++)
{
ListItem item = new ListItem();
SequenceData.VariableTimebaseSegment currentSeg = stepSegments[i];
item.repeats = currentSeg.NSegmentSamples;
item.offCounts = currentSeg.MasterSamplesPerSegmentSample / 2;
item.onCounts = currentSeg.MasterSamplesPerSegmentSample - item.offCounts;
// in assymmetric mode (spelling?), the clock duty cycle is not held at 50%, but rather the pulses are made to be
// 5 master cycles long at most. This is a workaround for the weird behavior of one of our fiber links
// for sharing the variable timebase signal.
if (assymetric)
{
if (item.onCounts > 5)
{
int difference = item.onCounts - 5;
item.onCounts = 5;
item.offCounts = item.offCounts + difference;
}
}
if (!item.isAllZeros())
{ // filter out any erroneously produced all-zero codes, since these have
// special meaning to the FPGA (they are "wait for retrigger" codes
listItems.Add(item);
}
}
}
}
// Add one final "pulse" at the end to trigger the dwell values. I'm basing this off the
// old variable timebase code that I found in the SequenceData program.
// This final pulse is made to be 100 us long at least, just to be on the safe side. (unless assymetric mode is on)
int minCounts = (int)(0.0001 / masterClockPeriod);
if (minCounts <= 0)
minCounts = 1;
ListItem finishItem = new ListItem(minCounts, minCounts, 1);
if (assymetric)
{
finishItem.onCounts = 5;
}
listItems.Add(finishItem);
nSegments = listItems.Count;
byte[] byteArray = new byte[listItems.Count * 16];
// This loop goes through the list items and creates
// the data as it is to be sent to the FPGA
// the data is a little shuffled because
// of the details of the byte order in
// piping data to the fpga.
for (int i = 0; i < listItems.Count; i++)
{
ListItem item = listItems[i];
byte[] onb = splitIntToBytes(item.onCounts);
byte[] offb = splitIntToBytes(item.offCounts);
byte[] repb = splitIntToBytes(item.repeats);
int offs = 16 * i;
byteArray[offs + 2] = onb[1];
byteArray[offs + 3] = onb[0];
byteArray[offs + 4] = onb[3];
byteArray[offs + 5] = onb[2];
byteArray[offs + 8] = offb[1];
byteArray[offs + 9] = offb[0];
byteArray[offs + 10] = offb[3];
byteArray[offs + 11] = offb[2];
byteArray[offs + 12] = repb[1];
byteArray[offs + 13] = repb[0];
byteArray[offs + 14] = repb[3];
byteArray[offs + 15] = repb[2];
}
//.........这里部分代码省略.........
示例2: createByteArray
/// <summary>
/// Create byte array for use in programming FPGA
/// </summary>
/// <param name="segments"></param>
/// <param name="sequence"></param>
/// <param name="nSegments"></param>
/// <param name="masterClockPeriod"></param>
/// <param name="assymetric"></param>
/// <returns></returns>
private static byte[] createByteArray(TimestepTimebaseSegmentCollection segments,
SequenceData sequence, out int nSegments, double masterClockPeriod, bool assymetric)
{
List<ListItem> listItems = new List<ListItem>();
for (int stepID = 0; stepID < sequence.TimeSteps.Count; stepID++)
{
if (sequence.TimeSteps[stepID].StepEnabled)
{
if (sequence.TimeSteps[stepID].RetriggerOptions.WaitForRetrigger)
{
uint waitTime = (uint)(sequence.TimeSteps[stepID].RetriggerOptions.RetriggerTimeout.getBaseValue() / masterClockPeriod);
uint retriggerFlags = 0;
if (sequence.TimeSteps[stepID].RetriggerOptions.RetriggerOnEdge)
retriggerFlags += 1;
if (!sequence.TimeSteps[stepID].RetriggerOptions.RetriggerOnNegativeValueOrEdge)
retriggerFlags += 2;
listItems.Add(new ListItem(waitTime, retriggerFlags, 0));
// counts = 0 is a special signal for WAIT_FOR_RETRIGGER mode
// in this mode, FPGA waits a maximum of on_counts master samples
// before moving on anyway.
// (unless on_counts = 0, in which case it never artificially retriggers)
// retrigger flags set if the FPGA will trigger on edge or on value
// and whether to trigger on positive or negative (edge or value)
}
List<SequenceData.VariableTimebaseSegment> stepSegments = segments[sequence.TimeSteps[stepID]];
for (int i = 0; i < stepSegments.Count; i++)
{
ListItem item = new ListItem();
SequenceData.VariableTimebaseSegment currentSeg = stepSegments[i];
item.repeats = (uint)currentSeg.NSegmentSamples;
item.offCounts = (uint)(currentSeg.MasterSamplesPerSegmentSample / 2);
item.onCounts = (uint)(currentSeg.MasterSamplesPerSegmentSample - item.offCounts);
// in assymmetric mode (spelling?), the clock duty cycle is not held at 50%, but rather the pulses are made to be
// 5 master cycles long at most. This is a workaround for the weird behavior of one of our fiber links
// for sharing the variable timebase signal.
if (assymetric)
{
if (item.onCounts > 5)
{
uint difference = item.onCounts - 5;
item.onCounts = 5;
item.offCounts = item.offCounts + difference;
}
}
if (!item.isAllZeros())
{ // filter out any erroneously produced all-zero codes, since these have
// special meaning to the FPGA (they are "wait for retrigger" codes
listItems.Add(item);
}
}
}
}
// Add one final "pulse" at the end to trigger the dwell values. I'm basing this off the
// old variable timebase code that I found in the SequenceData program.
// This final pulse is made to be 100 us long at least, just to be on the safe side. (unless assymetric mode is on)
int minCounts = (int)(0.0001 / masterClockPeriod);
if (minCounts <= 0)
minCounts = 1;
ListItem finishItem = new ListItem((uint)minCounts, (uint)minCounts, 1);
if (assymetric)
{
finishItem.onCounts = 5;
}
listItems.Add(finishItem);
nSegments = listItems.Count;
byte[] byteArray = new byte[listItems.Count * 16];
// This loop goes through the list items and creates
// the data as it is to be sent to the FPGA
// the data is a little shuffled because
// of the details of the byte order in
// piping data to the fpga.
// Each list item takes up 16 bytes in the output FIFO.
for (int i = 0; i < listItems.Count; i++)
{
//.........这里部分代码省略.........