C++ address_space类代码示例

void tms34061_device::write(address_space &space, int col, int row, int func, UINT8 data)
{
	offs_t offs;

	/* the function code determines what to do */
	switch (func)
	{
		/* both 0 and 2 map to register access */
		case 0:
		case 2:
			register_w(space, col, data);
			break;

		/* function 1 maps to XY access; col is the address adjustment */
		case 1:
			xypixel_w(space, col, data);
			break;

		/* function 3 maps to direct access */
		case 3:
			offs = ((row << m_rowshift) | col) & m_vrammask;
			if (m_regs[TMS34061_CONTROL2] & 0x0040)
				offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
			if (VERBOSE) logerror("%s:tms34061 direct (%04x) = %02x/%02x\n", space.machine().describe_context(), offs, data, m_latchdata);
			if (m_vram[offs] != data || m_latchram[offs] != m_latchdata)
			{
				m_vram[offs] = data;
				m_latchram[offs] = m_latchdata;
			}
			break;

		/* function 4 performs a shift reg transfer to VRAM */
		case 4:
			offs = col << m_rowshift;
			if (m_regs[TMS34061_CONTROL2] & 0x0040)
				offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
			offs &= m_vrammask;
			if (VERBOSE) logerror("%s:tms34061 shiftreg write (%04x)\n", space.machine().describe_context(), offs);

			memcpy(&m_vram[offs], m_shiftreg, (size_t)1 << m_rowshift);
			memset(&m_latchram[offs], m_latchdata, (size_t)1 << m_rowshift);
			break;

		/* function 5 performs a shift reg transfer from VRAM */
		case 5:
			offs = col << m_rowshift;
			if (m_regs[TMS34061_CONTROL2] & 0x0040)
				offs |= (m_regs[TMS34061_CONTROL2] & 3) << 16;
			offs &= m_vrammask;
			if (VERBOSE) logerror("%s:tms34061 shiftreg read (%04x)\n", space.machine().describe_context(), offs);

			m_shiftreg = &m_vram[offs];
			break;

		/* log anything else */
		default:
			logerror("%s:Unsupported TMS34061 function %d\n", space.machine().describe_context(), func);
			break;
	}
}

UINT16 m68307_sim::read_pbdat(address_space &space, UINT16 mem_mask)
{
	int pc = space.device().safe_pc();
	m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());

	if (m68k->m_m68307_portb_r)
	{
		// for general purpose bits, if configured as 'output' then anything output gets latched
		// and anything configured as input is read from the port
		UINT16 outputbits = m_pbddr;
		UINT16 inputbits = ~m_pbddr;
		UINT16 general_purpose_bits = ~m_pbcnt;

		UINT16 indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
		indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
		UINT16 outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)

		return (indat | outdat);
	}
	else
	{
		logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask);
	}
	return 0xffff;
}

address_map::address_map(const address_space &space, offs_t start, offs_t end, int bits, UINT64 unitmask, device_t &device, address_map_delegate submap_delegate)
	: m_spacenum(space.spacenum()),
		m_databits(space.data_width()),
		m_unmapval(space.unmap()),
		m_globalmask(space.bytemask())
{
	address_map_entry *e;
	switch(m_databits) {
	case 8:
		e = add(device, start, end, (address_map_entry8 *)NULL);
		break;
	case 16:
		e = add(device, start, end, (address_map_entry16 *)NULL);
		break;
	case 32:
		e = add(device, start, end, (address_map_entry32 *)NULL);
		break;
	case 64:
		e = add(device, start, end, (address_map_entry64 *)NULL);
		break;
	default:
		throw emu_fatalerror("Trying to dynamically map a device on a space with a corrupt databits width");
	}
	e->set_submap(DEVICE_SELF, submap_delegate, bits, unitmask);
}

void gt64xxx_device::perform_dma(address_space &space, int which)
{
	do
	{
		offs_t srcaddr = m_reg[GREG_DMA0_SOURCE + which];
		offs_t dstaddr = m_reg[GREG_DMA0_DEST + which];
		UINT32 bytesleft = m_reg[GREG_DMA0_COUNT + which] & 0xffff;
		int srcinc, dstinc;

		m_dma_active = which;
		m_reg[GREG_DMA0_CONTROL + which] |= 0x5000;

		/* determine src/dst inc */
		switch ((m_reg[GREG_DMA0_CONTROL + which] >> 2) & 3)
		{
			default:
			case 0:     srcinc = 1;     break;
			case 1:     srcinc = -1;    break;
			case 2:     srcinc = 0;     break;
		}
		switch ((m_reg[GREG_DMA0_CONTROL + which] >> 4) & 3)
		{
			default:
			case 0:     dstinc = 1;     break;
			case 1:     dstinc = -1;    break;
			case 2:     dstinc = 0;     break;
		}

		if (LOG_DMA)
			logerror("Performing DMA%d: src=%08X dst=%08X bytes=%04X sinc=%d dinc=%d\n", which, srcaddr, dstaddr, bytesleft, srcinc, dstinc);

		/* standard transfer */
			while (bytesleft > 0)
			{
				space.write_byte(dstaddr, space.read_byte(srcaddr));
				srcaddr += srcinc;
				dstaddr += dstinc;
				bytesleft--;
			}

		/* not verified, but seems logical these should be updated byte the end */
		m_reg[GREG_DMA0_SOURCE + which] = srcaddr;
		m_reg[GREG_DMA0_DEST + which] = dstaddr;
		m_reg[GREG_DMA0_COUNT + which] = (m_reg[GREG_DMA0_COUNT + which] & ~0xffff) | bytesleft;
		m_dma_active = -1;

		/* if we did not hit zero, punt and return later */
		if (bytesleft != 0)
			return;

		/* interrupt? */
		if (!(m_reg[GREG_DMA0_CONTROL + which] & 0x400))
		{
			m_reg[GREG_INT_STATE] |= 1 << (GINT_DMA0COMP_SHIFT + which);
			update_irqs();
		}
	} while (dma_fetch_next(space, which));

	m_reg[GREG_DMA0_CONTROL + which] &= ~0x5000;
}

/* Read/Write common */
void psion_state::io_rw(address_space &space, UINT16 offset)
{
	if (space.debugger_access())
		return;

	switch (offset & 0xffc0)
	{
	case 0xc0:
		/* switch off, CPU goes into standby mode */
		m_enable_nmi = 0;
		m_stby_pwr = 1;
		space.machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_HALT, 1);
		break;
	case 0x100:
		m_pulse = 1;
		break;
	case 0x140:
		m_pulse = 0;
		break;
	case 0x200:
		m_kb_counter = 0;
		break;
	case 0x180:
		beep_set_state(m_beep, 1);
		break;
	case 0x1c0:
		beep_set_state(m_beep, 0);
		break;
	case 0x240:
		if (offset == 0x260 && (m_rom_bank_count || m_ram_bank_count))
		{
			m_ram_bank=0;
			m_rom_bank=0;
			update_banks(machine());
		}
		else
			m_kb_counter++;
		break;
	case 0x280:
		if (offset == 0x2a0 && m_ram_bank_count)
		{
			m_ram_bank++;
			update_banks(machine());
		}
		else
			m_enable_nmi = 1;
		break;
	case 0x2c0:
		if (offset == 0x2e0 && m_rom_bank_count)
		{
			m_rom_bank++;
			update_banks(machine());
		}
		else
			m_enable_nmi = 0;
		break;
	}
}

address_map::address_map(const address_space &space, offs_t start, offs_t end, int bits, u64 unitmask, device_t &device, address_map_delegate submap_delegate)
	: m_spacenum(space.spacenum()),
		m_device(&device),
		m_databits(space.data_width()),
		m_unmapval(space.unmap()),
		m_globalmask(space.bytemask())
{
	range(start, end).set_submap(DEVICE_SELF, submap_delegate, bits, unitmask);
}

INLINE UINT16 galpani2_bg8_regs_r(address_space &space, offs_t offset, int n)
{
	galpani2_state *state = space.machine().driver_data<galpani2_state>();
	switch (offset * 2)
	{
		case 0x16:	return space.machine().rand() & 1;
		default:
			logerror("CPU #0 PC %06X : Warning, bg8 #%d screen reg %04X read\n",space.cpu->safe_pc(),_n_,offset*2);
	}
	return state->m_bg8_regs[_n_][offset];
}

debug_view_memory_source::debug_view_memory_source(const char *name, address_space &space)
	: debug_view_source(name, &space.device()),
		m_space(&space),
		m_memintf(dynamic_cast<device_memory_interface *>(&space.device())),
		m_base(nullptr),
		m_length(0),
		m_offsetxor(0),
		m_endianness(space.endianness()),
		m_prefsize(space.data_width() / 8)
{
}

void saturn_state::scu_single_transfer(address_space &space, UINT32 src, UINT32 dst,UINT8 *src_shift)
{
	UINT32 src_data;

	if(src & 1)
	{
		/* Road Blaster does a work ram h to color ram with offsetted source address, do some data rotation */
		src_data = ((space.read_dword(src & 0x07fffffc) & 0x00ffffff)<<8);
		src_data |= ((space.read_dword((src & 0x07fffffc)+4) & 0xff000000) >> 24);
		src_data >>= (*src_shift)*16;
	}

static void dragrace_update_misc_flags( address_space &space )
{
	dragrace_state *state = space.machine().driver_data<dragrace_state>();
	/* 0x0900 = set 3SPEED1         0x00000001
	 * 0x0901 = set 4SPEED1         0x00000002
	 * 0x0902 = set 5SPEED1         0x00000004
	 * 0x0903 = set 6SPEED1         0x00000008
	 * 0x0904 = set 7SPEED1         0x00000010
	 * 0x0905 = set EXPLOSION1      0x00000020
	 * 0x0906 = set SCREECH1        0x00000040
	 * 0x0920 - 0x0927 = clear 0x0900 - 0x0907

	 * 0x0909 = set KLEXPL1         0x00000200
	 * 0x090b = set MOTOR1          0x00000800
	 * 0x090c = set ATTRACT         0x00001000
	 * 0x090d = set LOTONE          0x00002000
	 * 0x090f = set Player 1 Start Lamp 0x00008000
	 * 0x0928 - 0x092f = clear 0x0908 - 0x090f

	 * 0x0910 = set 3SPEED2         0x00010000
	 * 0x0911 = set 4SPEED2         0x00020000
	 * 0x0912 = set 5SPEED2         0x00040000
	 * 0x0913 = set 6SPEED2         0x00080000
	 * 0x0914 = set 7SPEED2         0x00100000
	 * 0x0915 = set EXPLOSION2      0x00200000
	 * 0x0916 = set SCREECH2        0x00400000
	 * 0x0930 = clear 0x0910 - 0x0917

	 * 0x0919 = set KLEXPL2         0x02000000
	 * 0x091b = set MOTOR2          0x08000000
	 * 0x091d = set HITONE          0x20000000
	 * 0x091f = set Player 2 Start Lamp 0x80000000
	 * 0x0938 = clear 0x0918 - 0x091f
	 */
	set_led_status(space.machine(), 0, state->m_misc_flags & 0x00008000);
	set_led_status(space.machine(), 1, state->m_misc_flags & 0x80000000);

	discrete_sound_w(state->m_discrete, space, DRAGRACE_MOTOR1_DATA,  ~state->m_misc_flags & 0x0000001f);       // Speed1 data*
	discrete_sound_w(state->m_discrete, space, DRAGRACE_EXPLODE1_EN, (state->m_misc_flags & 0x00000020) ? 1: 0);    // Explosion1 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_SCREECH1_EN, (state->m_misc_flags & 0x00000040) ? 1: 0);    // Screech1 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_KLEXPL1_EN, (state->m_misc_flags & 0x00000200) ? 1: 0); // KLEXPL1 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_MOTOR1_EN, (state->m_misc_flags & 0x00000800) ? 1: 0);  // Motor1 enable

	discrete_sound_w(state->m_discrete, space, DRAGRACE_MOTOR2_DATA, (~state->m_misc_flags & 0x001f0000) >> 0x10);  // Speed2 data*
	discrete_sound_w(state->m_discrete, space, DRAGRACE_EXPLODE2_EN, (state->m_misc_flags & 0x00200000) ? 1: 0);    // Explosion2 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_SCREECH2_EN, (state->m_misc_flags & 0x00400000) ? 1: 0);    // Screech2 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_KLEXPL2_EN, (state->m_misc_flags & 0x02000000) ? 1: 0); // KLEXPL2 enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_MOTOR2_EN, (state->m_misc_flags & 0x08000000) ? 1: 0);  // Motor2 enable

	discrete_sound_w(state->m_discrete, space, DRAGRACE_ATTRACT_EN, (state->m_misc_flags & 0x00001000) ? 1: 0); // Attract enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_LOTONE_EN, (state->m_misc_flags & 0x00002000) ? 1: 0);  // LoTone enable
	discrete_sound_w(state->m_discrete, space, DRAGRACE_HITONE_EN, (state->m_misc_flags & 0x20000000) ? 1: 0);  // HiTone enable
}

inline void ti8x_update_bank(address_space &space, UINT8 bank, UINT8 *base, UINT8 page, bool is_ram)
{
	ti85_state *state = space.machine().driver_data<ti85_state>();
	static const char *const tag[] = {"bank1", "bank2", "bank3", "bank4"};

	state->membank(tag[bank&3])->set_base(base + (0x4000 * page));

	if (is_ram)
		space.install_write_bank(bank * 0x4000, bank * 0x4000 + 0x3fff, tag[bank&3]);
	else
		space.nop_write(bank * 0x4000, bank * 0x4000 + 0x3fff);
}

static UINT32 pm_io(address_space &space, int reg, int write, UINT32 d)
{
	mdsvp_state *state = space.machine().driver_data<mdsvp_state>();
	if (state->m_emu_status & SSP_PMC_SET)
	{
		state->m_pmac_read[write ? reg + 6 : reg] = state->m_pmc.d;
		state->m_emu_status &= ~SSP_PMC_SET;
		return 0;
	}

	// just in case
	if (state->m_emu_status & SSP_PMC_HAVE_ADDR) {
		state->m_emu_status &= ~SSP_PMC_HAVE_ADDR;
	}

	if (reg == 4 || (space.device().state().state_int(SSP_ST) & 0x60))
	{
		#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
		UINT16 *dram = (UINT16 *)state->m_dram;
		if (write)
		{
			int mode = state->m_pmac_write[reg]>>16;
			int addr = state->m_pmac_write[reg]&0xffff;
			if      ((mode & 0x43ff) == 0x0018) // DRAM
			{
				int inc = get_inc(mode);
				if (mode & 0x0400) {
						overwrite_write(&dram[addr], d);
				} else dram[addr] = d;
				state->m_pmac_write[reg] += inc;
			}
			else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
			{
				if (mode & 0x0400) {
						overwrite_write(&dram[addr], d);
				} else dram[addr] = d;
				state->m_pmac_write[reg] += (addr&1) ? 31 : 1;
			}
			else if ((mode & 0x47ff) == 0x001c) // IRAM
			{
				int inc = get_inc(mode);
				((UINT16 *)state->m_iram)[addr&0x3ff] = d;
				state->m_pmac_write[reg] += inc;
			}
			else
			{
				logerror("ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x\n",
						reg, mode, CADDR, d);
			}
		}
		else
		{

void lpc210x_device::write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask)
{
	switch (offset * 4)
	{
	case 0x0c:
		COMBINE_DATA(&m_TxPR[timer]);
		logerror("%08x Timer %d Prescale Register set to %08x\n", space.device().safe_pc(),timer, m_TxPR[timer]);
		break;

	default:
		logerror("%08x unhandled write timer %d offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, data, mem_mask);
	}
}

void m68307_sim::write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask)
{
	int pc = space.device().safe_pc();
	m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
	COMBINE_DATA(&m_pbdat);

	if (m68k->m_m68307_portb_w)
	{
		m68k->m_m68307_portb_w(space, false, data, mem_mask);
	}
	else
	{
		logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
	}
}

static UINT8 srtc_read( address_space &space, UINT16 addr )
{
	addr &= 0xffff;

	if (addr == 0x2800)
	{
		if (rtc_state.mode != RTCM_Read)
		{
			return 0x00;
		}

		if (rtc_state.index < 0)
		{
			srtc_update_time(space.machine());
			rtc_state.index++;
			return 0x0f;
		}
		else if (rtc_state.index > 12)
		{
			rtc_state.index = -1;
			return 0x0f;
		}
		else
		{
			return rtc_state.ram[rtc_state.index++];
		}
	}

	return snes_open_bus_r(space, 0);
}