C++ PPCEmuAssembler::add方法代码示例

// Store Multiple Words
// Writes consecutive words to memory from rS to r31
static bool
stmw(PPCEmuAssembler& a, Instruction instr)
{
   auto o = sign_extend<16, int32_t>(instr.d);
   if (instr.rA) {
      a.mov(a.ecx, a.ppcgpr[instr.rA]);
      a.add(a.ecx, o);
   } else {
      a.mov(a.ecx, o);
   }
   a.add(a.zcx, a.membase);
   
   for (int r = instr.rS, d = 0; r <= 31; ++r, d += 4) {
      a.mov(a.eax, a.ppcgpr[r]);
      a.bswap(a.eax);
      a.mov(asmjit::X86Mem(a.zcx, d), a.eax);
   }
   return true;
}

// Data Cache Block Zero
static bool
dcbz(PPCEmuAssembler& a, Instruction instr)
{
   auto src = a.allocGpTmp().r32();

   if (instr.rA == 0) {
      a.mov(src, 0);
   } else {
      a.mov(src, a.loadRegisterRead(a.gpr[instr.rA]));
   }

   a.add(src, a.loadRegisterRead(a.gpr[instr.rB]));

   // Align down
   a.and_(src, ~static_cast<uint32_t>(31));

   // Write 32 bytes of zero's there
   a.mov(asmjit::X86Mem(a.membaseReg, src, 0, 0, 8), 0);
   a.mov(asmjit::X86Mem(a.membaseReg, src, 0, 8, 8), 0);
   a.mov(asmjit::X86Mem(a.membaseReg, src, 0, 16, 8), 0);
   a.mov(asmjit::X86Mem(a.membaseReg, src, 0, 24, 8), 0);

   return true;
}

static bool
addGeneric(PPCEmuAssembler& a, Instruction instr)
{
   if (flags & AddSubtract) {
      return jit_fallback(a, instr);
   }

   bool recordCarry = false;
   bool recordOverflow = false;
   bool recordCond = false;

   if (flags & AddCarry) {
      recordCarry = true;
   }

   if (flags & AddAlwaysRecord) {
      recordOverflow = true;
      recordCond = true;
   } else if (flags & AddCheckRecord) {
      if (instr.oe) {
         recordOverflow = true;
      }

      if (instr.rc) {
         recordCond = true;
      }
   }

   if ((flags & AddZeroRA) && instr.rA == 0) {
      a.mov(a.eax, 0);
   } else {
      a.mov(a.eax, a.ppcgpr[instr.rA]);
   }

   if (flags & AddSubtract) {
      a.not_(a.eax);
   }

   if (flags & AddImmediate) {
      a.mov(a.ecx, sign_extend<16>(instr.simm));
   } else if (flags & AddToZero) {
      a.mov(a.ecx, 0);
   } else if (flags & AddToMinusOne) {
      a.mov(a.ecx, -1);
   } else {
      a.mov(a.ecx, a.ppcgpr[instr.rB]);
   }

   if (flags & AddShifted) {
      a.shl(a.ecx, 16);
   }

   // Mark x64 CF based on PPC CF
   if (flags & AddExtended) {
      a.mov(a.edx, a.ppcxer);
      a.and_(a.edx, XERegisterBits::Carry);
      a.add(a.edx, 0xffffffff);

      a.adc(a.eax, a.ecx);
   } else if (flags & AddSubtract) {
      a.stc();

      a.adc(a.eax, a.ecx);
   } else {
      a.add(a.eax, a.ecx);
   }

   if (recordCarry && recordOverflow) {
      a.mov(a.ecx, 0);
      a.setc(a.ecx.r8());
      a.mov(a.edx, 0);
      a.seto(a.edx.r8());

      a.shl(a.ecx, XERegisterBits::CarryShift);
      a.shl(a.edx, XERegisterBits::OverflowShift);
      a.or_(a.ecx, a.edx);
   } else if (recordCarry) {
      a.mov(a.ecx, 0);
      a.setc(a.ecx.r8());
      a.shl(a.ecx, XERegisterBits::CarryShift);
   } else if (recordOverflow) {
      a.mov(a.ecx, 0);
      a.seto(a.ecx.r8());
      a.shl(a.ecx, XERegisterBits::OverflowShift);
   }

   if (recordCarry || recordOverflow) {
      uint32_t mask = 0xFFFFFFFF;

      if (recordCarry) {
         mask &= ~XERegisterBits::Carry;
      }

      if (recordOverflow) {
         mask &= ~XERegisterBits::Overflow;
      }

      a.mov(a.edx, a.ppcxer);
      a.and_(a.edx, mask);
      a.or_(a.edx, a.ecx);
//.........这里部分代码省略.........

static bool
storeGeneric(PPCEmuAssembler& a, Instruction instr)
{
   if (flags & StoreConditional) {
      // Early out for if statement below.
      return jit_fallback(a, instr);
   }

   if ((flags & StoreZeroRA) && instr.rA == 0) {
      if (flags & StoreIndexed) {
         a.mov(a.ecx, a.ppcgpr[instr.rB]);
      } else {
         a.mov(a.ecx, sign_extend<16, int32_t>(instr.d));
      }
   } else {
      a.mov(a.ecx, a.ppcgpr[instr.rA]);

      if (flags & StoreIndexed) {
         a.add(a.ecx, a.ppcgpr[instr.rB]);
      } else {
         a.add(a.ecx, sign_extend<16, int32_t>(instr.d));
      }
   }

   if (flags & StoreConditional) {
      /*
      state->cr.cr0 = state->xer.so ? ConditionRegisterFlag::SummaryOverflow : 0;

      if (state->reserve) {
      // Store is succesful, clear reserve bit and set CR0[EQ]
      state->cr.cr0 |= ConditionRegisterFlag::Equal;
      state->reserve = false;
      } else {
      // Reserve bit is not set, do not write.
      return;
      }
      */
   }

   a.mov(a.zdx, a.zcx);
   a.add(a.zdx, a.membase);

   if (flags & StoreFloatAsInteger) {
      assert(sizeof(Type) == 4);
      a.mov(a.eax, a.ppcfprps[instr.rS][0]);
   } else if (std::is_floating_point<Type>::value) {
      if (flags & StoreSingle) {
         assert(sizeof(Type) == 4);
         a.mov(a.eax, a.ppcfprps[instr.rS][0]);
      }
      else {
         assert(sizeof(Type) == 8);
         a.mov(a.zax, a.ppcfpr[instr.rS]);
      }
   } else {
      if (sizeof(Type) == 1) {
         a.mov(a.eax.r8(), a.ppcgpr[instr.rS]);
      } else if (sizeof(Type) == 2) {
         a.mov(a.eax.r16(), a.ppcgpr[instr.rS]);
      } else if (sizeof(Type) == 4) {
         a.mov(a.eax, a.ppcgpr[instr.rS]);
      } else {
         assert(0);
      }
   }

   if (!(flags & StoreByteReverse)) {
      if (sizeof(Type) == 1) {
         // Inverted reverse logic means we have
         //    to check for this but do nothing.
      } else if (sizeof(Type) == 2) {
         a.xchg(a.eax.r8Hi(), a.eax.r8Lo());
      } else if (sizeof(Type) == 4) {
         a.bswap(a.eax);
      } else if (sizeof(Type) == 8) {
         a.bswap(a.zax);
      } else {
         assert(0);
      }
   }

   if (sizeof(Type) == 1) {
      a.mov(asmjit::X86Mem(a.zdx, 0), a.eax.r8());
   } else if (sizeof(Type) == 2) {
      a.mov(asmjit::X86Mem(a.zdx, 0), a.eax.r16());
   } else if (sizeof(Type) == 4) {
      a.mov(asmjit::X86Mem(a.zdx, 0), a.eax);
   } else if (sizeof(Type) == 8) {
      a.mov(asmjit::X86Mem(a.zdx, 0), a.zax);
   } else {
      assert(0);
   }

   if (flags & StoreUpdate) {
      a.mov(a.ppcgpr[instr.rA], a.ecx);
   }

   return true;
}

static bool
loadGeneric(PPCEmuAssembler& a, Instruction instr)
{
   if ((flags & LoadZeroRA) && instr.rA == 0) {
      a.mov(a.ecx, 0u);
   }
   else {
      a.mov(a.ecx, a.ppcgpr[instr.rA]);
   }

   if (flags & LoadIndexed) {
      a.add(a.ecx, a.ppcgpr[instr.rB]);
   }
   else {
      a.add(a.ecx, sign_extend<16, int32_t>(instr.d));
   }

   a.mov(a.zdx, a.zcx);
   a.add(a.zdx, a.membase);
   if (sizeof(Type) == 1) {
      a.mov(a.eax, 0);
      a.mov(a.eax.r8(), asmjit::X86Mem(a.zdx, 0));
   } else if (sizeof(Type) == 2) {
      a.mov(a.eax, 0);
      a.mov(a.eax.r16(), asmjit::X86Mem(a.zdx, 0));
      if (!(flags & LoadByteReverse)) {
         a.xchg(a.eax.r8Hi(), a.eax.r8Lo());
      }
   } else if (sizeof(Type) == 4) {
      a.mov(a.eax, asmjit::X86Mem(a.zdx, 0));
      if (!(flags & LoadByteReverse)) {
         a.bswap(a.eax);
      }
   } else if (sizeof(Type) == 8) {
      a.mov(a.zax, asmjit::X86Mem(a.zdx, 0));
      if (!(flags & LoadByteReverse)) {
         a.bswap(a.zax);
      }
   } else {
      assert(0);
   }

   if (std::is_floating_point<Type>::value) {
      if (flags & LoadPairedSingles) {
         a.mov(a.ppcfprps[instr.rD][0], a.eax);
         a.mov(a.ppcfprps[instr.rD][1], a.eax);
      }
      else {
         assert(sizeof(Type) == 8);
         a.mov(a.ppcfpr[instr.rD], a.zax);
      }
   }
   else {
      if (flags & LoadSignExtend) {
         assert(sizeof(Type) == 2);
         a.movsx(a.eax, a.eax.r16());
      }

      a.mov(a.ppcgpr[instr.rD], a.eax);
   }

   if (flags & LoadReserve) {
      a.mov(a.ppcreserve, 1u);
      a.mov(a.ppcreserveAddress, a.ecx);
   }

   if (flags & LoadUpdate) {
      a.mov(a.ppcgpr[instr.rA], a.ecx);
   }
   return true;
}