本文整理汇总了C++中MemoryBase::page_allocator方法的典型用法代码示例。如果您正苦于以下问题：C++ MemoryBase::page_allocator方法的具体用法？C++ MemoryBase::page_allocator怎么用？C++ MemoryBase::page_allocator使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类MemoryBase的用法示例。
在下文中一共展示了MemoryBase::page_allocator方法的1个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: id
Core::Core(const Config& configs, int coreid,
const char* trace_fname, function<bool(Request)> send_next,
Cache* llc, std::shared_ptr<CacheSystem> cachesys, MemoryBase& memory)
: id(coreid), no_core_caches(!configs.has_core_caches()),
no_shared_cache(!configs.has_l3_cache()),
llc(llc), trace(trace_fname), memory(memory)
{
// Build cache hierarchy
if (no_core_caches) {
send = send_next;
} else {
// L2 caches[0]
caches.emplace_back(new Cache(
l2_size, l2_assoc, l2_blocksz, l2_mshr_num,
Cache::Level::L2, cachesys));
// L1 caches[1]
caches.emplace_back(new Cache(
l1_size, l1_assoc, l1_blocksz, l1_mshr_num,
Cache::Level::L1, cachesys));
send = bind(&Cache::send, caches[1].get(), placeholders::_1);
if (llc != nullptr) {
caches[0]->concatlower(llc);
}
caches[1]->concatlower(caches[0].get());
}
if (no_core_caches) {
more_reqs = trace.get_filtered_request(
bubble_cnt, req_addr, req_type);
req_addr = memory.page_allocator(req_addr, id);
} else {
more_reqs = trace.get_unfiltered_request(
bubble_cnt, req_addr, req_type);
req_addr = memory.page_allocator(req_addr, id);
}
// set expected limit instruction for calculating weighted speedup
expected_limit_insts = configs.get_expected_limit_insts();
// regStats
record_cycs.name("record_cycs_core_" + to_string(id))
.desc("Record cycle number for calculating weighted speedup. (Only valid when expected limit instruction number is non zero in config file.)")
.precision(0)
;
record_insts.name("record_insts_core_" + to_string(id))
.desc("Retired instruction number when record cycle number. (Only valid when expected limit instruction number is non zero in config file.)")
.precision(0)
;
memory_access_cycles.name("memory_access_cycles_core_" + to_string(id))
.desc("memory access cycles in memory time domain")
.precision(0)
;
memory_access_cycles = 0;
cpu_inst.name("cpu_instructions_core_" + to_string(id))
.desc("cpu instruction number")
.precision(0)
;
cpu_inst = 0;
}