本文整理汇总了C++中HSim__s6::constructPorts方法的典型用法代码示例。如果您正苦于以下问题：C++ HSim__s6::constructPorts方法的具体用法？C++ HSim__s6::constructPorts怎么用？C++ HSim__s6::constructPorts使用的例子？那么, 这里精选的方法代码示例或许可以为您提供帮助。您也可以进一步了解该方法所在类HSim__s6的用法示例。
在下文中一共展示了HSim__s6::constructPorts方法的6个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
HSim__s6 * topvh = 0;
topvh = new Work_nandandgate_tb_testbench_arch("NANDANDGate_tb");
topvh->constructPorts();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}示例2: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
HSim__s6 * topvh = 0;
topvh = new Work_notgate_behavioral("notgate");
topvh->constructPorts();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}示例3: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
HSim__s6 * topvh = 0;
topvh = new Work_waveencoder_testbench_arch("WaveEncoder");
topvh->constructPorts();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}示例4: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
HSim__s6 * topvh = 0;
extern HSim__s6 * createWork_w_alublock_testbench_arch(const char*);
topvh = createWork_w_alublock_testbench_arch("w_alublock");
topvh->constructPorts();
topvh->checkTopLevelPortsConstrainted();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}示例5: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
(*cfgvh).registerFuseLibList("");
HSim__s6 * topvh = 0;
extern HSim__s6 * createWork_q2vhdlkmaptestbench_vhd_behavior(const char*);
topvh = createWork_q2vhdlkmaptestbench_vhd_behavior("Q2VHDLKmapTestBench_vhd");
topvh->constructPorts();
topvh->checkTopLevelPortsConstrainted();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}示例6: topModuleInstantiate
HSimConfigDecl * topModuleInstantiate() {
HSimConfigDecl * cfgvh = 0;
cfgvh = new HSimConfigDecl("default");
(*cfgvh).registerFuseLibList("unisims_ver");
HSim__s6 * topvh = 0;
extern HSim__s6 * createWork_test1_testbench_arch(const char*);
topvh = createWork_test1_testbench_arch("test1");
topvh->constructPorts();
topvh->checkTopLevelPortsConstrainted();
topvh->vhdlArchImplement();
topvh->architectureInstantiate(cfgvh);
addChild(topvh);
return cfgvh;
}