本文整理汇总了C++中GenTreePtr类的典型用法代码示例。如果您正苦于以下问题:C++ GenTreePtr类的具体用法?C++ GenTreePtr怎么用?C++ GenTreePtr使用的例子?那么, 这里精选的类代码示例或许可以为您提供帮助。
在下文中一共展示了GenTreePtr类的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: optBlockCopyPropPopStacks
/**************************************************************************************
*
* Corresponding to the live definition pushes, pop the stack as we finish a sub-paths
* of the graph originating from the block. Refer SSA renaming for any additional info.
* "curSsaName" tracks the currently live definitions.
*/
void Compiler::optBlockCopyPropPopStacks(BasicBlock* block, LclNumToGenTreePtrStack* curSsaName)
{
for (GenTreePtr stmt = block->bbTreeList; stmt; stmt = stmt->gtNext)
{
for (GenTreePtr tree = stmt->gtStmt.gtStmtList; tree; tree = tree->gtNext)
{
if (!tree->IsLocal())
{
continue;
}
unsigned lclNum = tree->gtLclVarCommon.gtLclNum;
if (fgExcludeFromSsa(lclNum))
{
continue;
}
if (tree->gtFlags & GTF_VAR_DEF)
{
GenTreePtrStack* stack = nullptr;
curSsaName->Lookup(lclNum, &stack);
stack->Pop();
if (stack->Height() == 0)
{
curSsaName->Remove(lclNum);
}
}
}
}
}
示例2: genDoneAddressableFloat
void CodeGen::genDoneAddressableFloat(GenTreePtr tree,
regMaskTP addrRegInt,
regMaskTP addrRegFlt,
RegSet::KeepReg keptReg)
{
assert(!(addrRegInt && addrRegFlt));
if (addrRegInt)
{
return genDoneAddressable(tree, addrRegInt, keptReg);
}
else if (addrRegFlt)
{
if (keptReg == RegSet::KEEP_REG)
{
for (regNumber r = REG_FP_FIRST; r != REG_NA; r = regNextOfType(r, tree->TypeGet()))
{
regMaskTP mask = genRegMaskFloat(r, tree->TypeGet());
// some masks take up more than one bit
if ((mask & addrRegFlt) == mask)
{
regSet.SetUsedRegFloat(tree, false);
}
}
}
}
}
示例3: genTypeSize
//------------------------------------------------------------------------
// LowerRotate: Lower GT_ROL and GT_ROR nodes.
//
// Arguments:
// tree - the node to lower
//
// Return Value:
// None.
//
void Lowering::LowerRotate(GenTreePtr tree)
{
if (tree->OperGet() == GT_ROL)
{
// There is no ROL instruction on ARM. Convert ROL into ROR.
GenTreePtr rotatedValue = tree->gtOp.gtOp1;
unsigned rotatedValueBitSize = genTypeSize(rotatedValue->gtType) * 8;
GenTreePtr rotateLeftIndexNode = tree->gtOp.gtOp2;
if (rotateLeftIndexNode->IsCnsIntOrI())
{
ssize_t rotateLeftIndex = rotateLeftIndexNode->gtIntCon.gtIconVal;
ssize_t rotateRightIndex = rotatedValueBitSize - rotateLeftIndex;
rotateLeftIndexNode->gtIntCon.gtIconVal = rotateRightIndex;
}
else
{
GenTreePtr tmp =
comp->gtNewOperNode(GT_NEG, genActualType(rotateLeftIndexNode->gtType), rotateLeftIndexNode);
BlockRange().InsertAfter(rotateLeftIndexNode, tmp);
tree->gtOp.gtOp2 = tmp;
}
tree->ChangeOper(GT_ROR);
}
ContainCheckShiftRotate(tree->AsOp());
}
示例4: genCodeForTreeFloat
void CodeGen::genCodeForTreeFloat(GenTreePtr tree,
RegSet::RegisterPreference *pref)
{
genTreeOps oper;
unsigned kind;
assert(tree);
assert(tree->gtOper != GT_STMT);
// What kind of node do we have?
oper = tree->OperGet();
kind = tree->OperKind();
if (kind & GTK_CONST)
{
genFloatConst(tree, pref);
}
else if (kind & GTK_LEAF)
{
genFloatLeaf(tree, pref);
}
else if (kind & GTK_SMPOP)
{
genFloatSimple(tree, pref);
}
else
{
assert(oper == GT_CALL);
genCodeForCall(tree, true);
}
}
示例5: address
//------------------------------------------------------------------------
// DecomposeInd: Decompose GT_IND.
//
// Arguments:
// use - the LIR::Use object for the def that needs to be decomposed.
//
// Return Value:
// The next node to process.
//
GenTree* DecomposeLongs::DecomposeInd(LIR::Use& use)
{
GenTree* indLow = use.Def();
LIR::Use address(Range(), &indLow->gtOp.gtOp1, indLow);
address.ReplaceWithLclVar(m_compiler, m_blockWeight);
JITDUMP("[DecomposeInd]: Saving addr tree to a temp var:\n");
DISPTREERANGE(Range(), address.Def());
// Change the type of lower ind.
indLow->gtType = TYP_INT;
// Create tree of ind(addr+4)
GenTreePtr addrBase = indLow->gtGetOp1();
GenTreePtr addrBaseHigh = new (m_compiler, GT_LCL_VAR)
GenTreeLclVar(GT_LCL_VAR, addrBase->TypeGet(), addrBase->AsLclVarCommon()->GetLclNum(), BAD_IL_OFFSET);
GenTreePtr addrHigh =
new (m_compiler, GT_LEA) GenTreeAddrMode(TYP_REF, addrBaseHigh, nullptr, 0, genTypeSize(TYP_INT));
GenTreePtr indHigh = new (m_compiler, GT_IND) GenTreeIndir(GT_IND, TYP_INT, addrHigh, nullptr);
m_compiler->lvaIncRefCnts(addrBaseHigh);
Range().InsertAfter(indLow, addrBaseHigh, addrHigh, indHigh);
return FinalizeDecomposition(use, indLow, indHigh);
}
示例6: IsBinOpMonotonicallyIncreasing
bool RangeCheck::IsBinOpMonotonicallyIncreasing(GenTreePtr op1, GenTreePtr op2, genTreeOps oper, SearchPath* path)
{
JITDUMP("[RangeCheck::IsBinOpMonotonicallyIncreasing] %p, %p\n", dspPtr(op1), dspPtr(op2));
// Check if we have a var + const.
if (op2->OperGet() == GT_LCL_VAR)
{
jitstd::swap(op1, op2);
}
if (op1->OperGet() != GT_LCL_VAR)
{
JITDUMP("Not monotonic because op1 is not lclVar.\n");
return false;
}
switch (op2->OperGet())
{
case GT_LCL_VAR:
return IsMonotonicallyIncreasing(op1, path) &&
IsMonotonicallyIncreasing(op2, path);
case GT_CNS_INT:
return oper == GT_ADD && op2->AsIntConCommon()->IconValue() >= 0 &&
IsMonotonicallyIncreasing(op1, path);
default:
JITDUMP("Not monotonic because expression is not recognized.\n");
return false;
}
}
示例7: TreeNodeInfoInitCmp
//------------------------------------------------------------------------
// TreeNodeInfoInitCmp: Lower a GT comparison node.
//
// Arguments:
// tree - the node to lower
//
// Return Value:
// None.
//
void Lowering::TreeNodeInfoInitCmp(GenTreePtr tree)
{
ContainCheckCompare(tree->AsOp());
TreeNodeInfo* info = &(tree->gtLsraInfo);
info->srcCount = tree->gtOp.gtOp2->isContained() ? 1 : 2;
info->dstCount = tree->OperIs(GT_CMP) ? 0 : 1;
}
示例8: switch
GenTreePtr CodeGen::genMakeAddressableFloat(GenTreePtr tree,
regMaskTP * regMaskIntPtr,
regMaskTP * regMaskFltPtr,
bool bCollapseConstantDoubles)
{
*regMaskIntPtr = *regMaskFltPtr = 0;
switch (tree->OperGet())
{
case GT_LCL_VAR:
genMarkLclVar(tree);
__fallthrough;
case GT_REG_VAR:
case GT_LCL_FLD:
case GT_CLS_VAR:
return tree;
case GT_IND:
// Try to make the address directly addressable
if (genMakeIndAddrMode(tree->gtOp.gtOp1,
tree,
false,
RBM_ALLFLOAT,
RegSet::KEEP_REG,
regMaskIntPtr,
false))
{
genUpdateLife(tree);
return tree;
}
else
{
GenTreePtr addr = tree;
tree = tree->gtOp.gtOp1;
genCodeForTree(tree, 0);
regSet.rsMarkRegUsed(tree, addr);
*regMaskIntPtr = genRegMask(tree->gtRegNum);
return addr;
}
// fall through
default:
genCodeForTreeFloat(tree);
regSet.SetUsedRegFloat(tree, true);
// update mask
*regMaskFltPtr = genRegMaskFloat(tree->gtRegNum, tree->TypeGet());
return tree;
break;
}
}
示例9: IsLockedRegFloat
bool RegSet::IsLockedRegFloat(GenTreePtr tree)
{
/* The value must be sitting in a register */
assert(tree);
assert(tree->gtFlags & GTF_REG_VAL);
assert(varTypeIsFloating(tree->TypeGet()));
regMaskTP regMask = genRegMaskFloat(tree->gtRegNum, tree->TypeGet());
return (rsGetMaskLock() & regMask) == regMask;
}
示例10: gcMarkRegPtrVal
void GCInfo::gcMarkRegPtrVal(GenTreePtr tree)
{
if (varTypeIsGC(tree->TypeGet()))
{
if (tree->gtOper == GT_LCL_VAR)
compiler->codeGen->genMarkLclVar(tree);
if (tree->InReg())
{
gcMarkRegSetNpt(genRegMask(tree->gtRegNum));
}
}
}
示例11: genKeepAddressableFloat
void CodeGen::genKeepAddressableFloat(GenTreePtr tree, regMaskTP * regMaskIntPtr, regMaskTP * regMaskFltPtr)
{
regMaskTP regMaskInt, regMaskFlt;
regMaskInt = *regMaskIntPtr;
regMaskFlt = *regMaskFltPtr;
*regMaskIntPtr = *regMaskFltPtr = 0;
switch (tree->OperGet())
{
case GT_REG_VAR:
// If register has been spilled, unspill it
if (tree->gtFlags & GTF_SPILLED)
{
UnspillFloat(&compiler->lvaTable[tree->gtLclVarCommon.gtLclNum]);
}
break;
case GT_CNS_DBL:
if (tree->gtFlags & GTF_SPILLED)
{
UnspillFloat(tree);
}
*regMaskFltPtr = genRegMaskFloat(tree->gtRegNum, tree->TypeGet());
break;
case GT_LCL_FLD:
case GT_LCL_VAR:
case GT_CLS_VAR:
break;
case GT_IND:
if (regMaskFlt == RBM_NONE)
{
*regMaskIntPtr = genKeepAddressable(tree, regMaskInt, 0);
*regMaskFltPtr = 0;
return;
}
__fallthrough;
default:
*regMaskIntPtr = 0;
if (tree->gtFlags & GTF_SPILLED)
{
UnspillFloat(tree);
}
*regMaskFltPtr = genRegMaskFloat(tree->gtRegNum, tree->TypeGet());
break;
}
}
示例12: ContainCheckCast
//------------------------------------------------------------------------
// ContainCheckCast: determine whether the source of a CAST node should be contained.
//
// Arguments:
// node - pointer to the node
//
void Lowering::ContainCheckCast(GenTreeCast* node)
{
#ifdef _TARGET_ARM_
GenTreePtr castOp = node->CastOp();
var_types castToType = node->CastToType();
var_types srcType = castOp->TypeGet();
if (varTypeIsLong(castOp))
{
assert(castOp->OperGet() == GT_LONG);
MakeSrcContained(node, castOp);
}
#endif // _TARGET_ARM_
}
示例13: TreeNodeInfoInitGCWriteBarrier
void Lowering::TreeNodeInfoInitGCWriteBarrier(GenTree* tree)
{
GenTreePtr dst = tree;
GenTreePtr addr = tree->gtOp.gtOp1;
GenTreePtr src = tree->gtOp.gtOp2;
if (addr->OperGet() == GT_LEA)
{
// In the case where we are doing a helper assignment, if the dst
// is an indir through an lea, we need to actually instantiate the
// lea in a register
GenTreeAddrMode* lea = addr->AsAddrMode();
short leaSrcCount = 0;
if (lea->Base() != nullptr)
{
leaSrcCount++;
}
if (lea->Index() != nullptr)
{
leaSrcCount++;
}
lea->gtLsraInfo.srcCount = leaSrcCount;
lea->gtLsraInfo.dstCount = 1;
}
#if NOGC_WRITE_BARRIERS
NYI_ARM("NOGC_WRITE_BARRIERS");
// For the NOGC JIT Helper calls
//
// the 'addr' goes into x14 (REG_WRITE_BARRIER_DST_BYREF)
// the 'src' goes into x15 (REG_WRITE_BARRIER)
//
addr->gtLsraInfo.setSrcCandidates(m_lsra, RBM_WRITE_BARRIER_DST_BYREF);
src->gtLsraInfo.setSrcCandidates(m_lsra, RBM_WRITE_BARRIER);
#else
// For the standard JIT Helper calls
// op1 goes into REG_ARG_0 and
// op2 goes into REG_ARG_1
//
addr->gtLsraInfo.setSrcCandidates(m_lsra, RBM_ARG_0);
src->gtLsraInfo.setSrcCandidates(m_lsra, RBM_ARG_1);
#endif // NOGC_WRITE_BARRIERS
// Both src and dst must reside in a register, which they should since we haven't set
// either of them as contained.
assert(addr->gtLsraInfo.dstCount == 1);
assert(src->gtLsraInfo.dstCount == 1);
}
示例14: genRegVarDiesInSubTreeWorker
Compiler::fgWalkResult CodeGen::genRegVarDiesInSubTreeWorker(GenTreePtr* pTree, Compiler::fgWalkData* data)
{
GenTreePtr tree = *pTree;
genRegVarDiesInSubTreeData* pData = (genRegVarDiesInSubTreeData*)data->pCallbackData;
// if it's dying, just rename the register, else load it normally
if (tree->IsRegVar() && tree->IsRegVarDeath() && tree->gtRegVar.gtRegNum == pData->reg)
{
pData->result = true;
return Compiler::WALK_ABORT;
}
return Compiler::WALK_CONTINUE;
}
示例15: genAssignArithFloat
regNumber CodeGen::genAssignArithFloat(genTreeOps oper,
GenTreePtr dst, regNumber dstreg,
GenTreePtr src, regNumber srcreg)
{
regNumber result;
// dst should be a regvar or memory
if (dst->IsRegVar())
{
regNumber reg = dst->gtRegNum;
if (src->IsRegVar())
{
inst_RV_RV(ins_MathOp(oper, dst->gtType), reg, src->gtRegNum, dst->gtType);
}
else
{
inst_RV_TT(ins_MathOp(oper, dst->gtType), reg, src, 0, EmitSize(dst));
}
result = reg;
}
else // dst in memory
{
// since this is an asgop the ACTUAL destination is memory
// but it is also one of the sources and SSE ops do not allow mem dests
// so we have loaded it into a reg, and that is what dstreg represents
assert(dstreg != REG_NA);
if ( (src->InReg()))
{
inst_RV_RV(ins_MathOp(oper, dst->gtType), dstreg, src->gtRegNum, dst->gtType);
}
else
{
//mem mem operation
inst_RV_TT(ins_MathOp(oper, dst->gtType), dstreg, src, 0, EmitSize(dst));
}
dst->gtFlags &= ~GTF_REG_VAL; // ???
inst_TT_RV(ins_FloatStore(dst->gtType), dst, dstreg, 0, EmitSize(dst));
result = REG_NA;
}
return result;
}