C++ DagInit类代码示例

void SetTheory::evaluate(Init *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) {
  // A def in a list can be a just an element, or it may expand.
  if (DefInit *Def = dyn_cast<DefInit>(Expr)) {
    if (const RecVec *Result = expand(Def->getDef()))
      return Elts.insert(Result->begin(), Result->end());
    Elts.insert(Def->getDef());
    return;
  }

  // Lists simply expand.
  if (ListInit *LI = dyn_cast<ListInit>(Expr))
    return evaluate(LI->begin(), LI->end(), Elts, Loc);

  // Anything else must be a DAG.
  DagInit *DagExpr = dyn_cast<DagInit>(Expr);
  if (!DagExpr)
    PrintFatalError(Loc, "Invalid set element: " + Expr->getAsString());
  DefInit *OpInit = dyn_cast<DefInit>(DagExpr->getOperator());
  if (!OpInit)
    PrintFatalError(Loc, "Bad set expression: " + Expr->getAsString());
  auto I = Operators.find(OpInit->getDef()->getName());
  if (I == Operators.end())
    PrintFatalError(Loc, "Unknown set operator: " + Expr->getAsString());
  I->second->apply(*this, DagExpr, Elts, Loc);
}

std::vector<std::string>
InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
  std::vector<std::string> Result;
  
  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
    // Handle aggregate operands and normal operands the same way by expanding
    // either case into a list of operands for this op.
    std::vector<CodeGenInstruction::OperandInfo> OperandList;

    // This might be a multiple operand thing.  Targets like X86 have
    // registers in their multi-operand operands.  It may also be an anonymous
    // operand, which has a single operand, but no declared class for the
    // operand.
    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
    
    if (!MIOI || MIOI->getNumArgs() == 0) {
      // Single, anonymous, operand.
      OperandList.push_back(Inst.OperandList[i]);
    } else {
      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
        OperandList.push_back(Inst.OperandList[i]);

        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
        OperandList.back().Rec = OpR;
      }
    }

    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
      Record *OpR = OperandList[j].Rec;
      std::string Res;
      
      if (OpR->isSubClassOf("RegisterClass"))
        Res += getQualifiedName(OpR) + "RegClassID, ";
      else
        Res += "0, ";
      // Fill in applicable flags.
      Res += "0";
        
      // Ptr value whose register class is resolved via callback.
      if (OpR->getName() == "ptr_rc")
        Res += "|(1<<TOI::LookupPtrRegClass)";

      // Predicate operands.  Check to see if the original unexpanded operand
      // was of type PredicateOperand.
      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
        Res += "|(1<<TOI::Predicate)";
        
      // Optional def operands.  Check to see if the original unexpanded operand
      // was of type OptionalDefOperand.
      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
        Res += "|(1<<TOI::OptionalDef)";

      // Fill in constraint info.
      Res += ", " + Inst.OperandList[i].Constraints[j];
      Result.push_back(Res);
    }
  }

  return Result;
}

void SetTheory::evaluate(Init *Expr, RecSet &Elts) {
  // A def in a list can be a just an element, or it may expand.
  if (DefInit *Def = dynamic_cast<DefInit*>(Expr)) {
    if (const RecVec *Result = expand(Def->getDef()))
      return Elts.insert(Result->begin(), Result->end());
    Elts.insert(Def->getDef());
    return;
  }

  // Lists simply expand.
  if (ListInit *LI = dynamic_cast<ListInit*>(Expr))
    return evaluate(LI->begin(), LI->end(), Elts);

  // Anything else must be a DAG.
  DagInit *DagExpr = dynamic_cast<DagInit*>(Expr);
  if (!DagExpr)
    throw "Invalid set element: " + Expr->getAsString();
  DefInit *OpInit = dynamic_cast<DefInit*>(DagExpr->getOperator());
  if (!OpInit)
    throw "Bad set expression: " + Expr->getAsString();
  Operator *Op = Operators.lookup(OpInit->getDef()->getName());
  if (!Op)
    throw "Unknown set operator: " + Expr->getAsString();
  Op->apply(*this, DagExpr, Elts);
}

unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const {
    if (!isRecord())
        return 1;

    Record *Rec = getRecord();
    if (!Rec->isSubClassOf("Operand"))
        return 1;

    DagInit *MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
    if (MIOpInfo->getNumArgs() == 0) {
        // Unspecified, so it defaults to 1
        return 1;
    }

    return MIOpInfo->getNumArgs();
}

std::pair<unsigned,unsigned> 
CodeGenInstruction::ParseOperandName(const std::string &Op,
                                     bool AllowWholeOp) {
  if (Op.empty() || Op[0] != '$')
    throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
  
  std::string OpName = Op.substr(1);
  std::string SubOpName;
  
  // Check to see if this is $foo.bar.
  std::string::size_type DotIdx = OpName.find_first_of(".");
  if (DotIdx != std::string::npos) {
    SubOpName = OpName.substr(DotIdx+1);
    if (SubOpName.empty())
      throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
    OpName = OpName.substr(0, DotIdx);
  }
  
  unsigned OpIdx = getOperandNamed(OpName);

  if (SubOpName.empty()) {  // If no suboperand name was specified:
    // If one was needed, throw.
    if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
        SubOpName.empty())
      throw TheDef->getName() + ": Illegal to refer to"
            " whole operand part of complex operand '" + Op + "'";
  
    // Otherwise, return the operand.
    return std::make_pair(OpIdx, 0U);
  }
  
  // Find the suboperand number involved.
  DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo;
  if (MIOpInfo == 0)
    throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
  
  // Find the operand with the right name.
  for (unsigned i = 0, e = MIOpInfo->getNumArgs(); i != e; ++i)
    if (MIOpInfo->getArgName(i) == SubOpName)
      return std::make_pair(OpIdx, i);

  // Otherwise, didn't find it!
  throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
}

// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
  SubRegMap &SRM = SubReg[Reg];
  if (!SRM.empty())
    return SRM;
  std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
  std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
  if (SubRegs.size() != Indices.size())
    throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";

  // First insert the direct subregs and make sure they are fully indexed.
  for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
    if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
      throw "SubRegIndex " + Indices[i]->getName()
        + " appears twice in Register " + Reg->getName();
    inferSubRegIndices(SubRegs[i]);
  }

  // Keep track of inherited subregs and how they can be reached.
  // Register -> (SubRegIndex, SubRegIndex)
  typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
  OrphanMap Orphans;

  // Clone inherited subregs. Here the order is important - earlier subregs take
  // precedence.
  for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
    SubRegMap &M = SubReg[SubRegs[i]];
    for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
      if (!SRM.insert(*si).second)
        Orphans[si->second] = std::make_pair(Indices[i], si->first);
  }

  // Finally process the composites.
  ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
  for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
    DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
    if (!Pat)
      throw "Invalid dag '" + Comps->getElement(i)->getAsString()
        + "' in CompositeIndices";
    DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
    if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
      throw "Invalid SubClassIndex in " + Pat->getAsString();

    // Resolve list of subreg indices into R2.
    Record *R2 = Reg;
    for (DagInit::const_arg_iterator di = Pat->arg_begin(),
         de = Pat->arg_end(); di != de; ++di) {
      DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
      if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
        throw "Invalid SubClassIndex in " + Pat->getAsString();
      SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
      if (ni == SubReg[R2].end())
        throw "Composite " + Pat->getAsString() + " refers to bad index in "
          + R2->getName();
      R2 = ni->second;
    }

    // Insert composite index. Allow overriding inherited indices etc.
    SRM[BaseIdxInit->getDef()] = R2;

    // R2 is now directly addressable, no longer an orphan.
    Orphans.erase(R2);
  }

  // Now, Orphans contains the inherited subregisters without a direct index.
  if (!Orphans.empty()) {
    errs() << "Error: Register " << getQualifiedName(Reg)
           << " inherited subregisters without an index:\n";
    for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
         ++i) {
      errs() << "  " << getQualifiedName(i->first)
             << " = " << i->second.first->getName()
             << ", " << i->second.second->getName() << "\n";
    }
    abort();
  }
  return SRM;
}

InvTreePatternNode *InvTreePattern::ParseTreePattern(Init *TheInit, StringRef OpName) {
  if (DefInit *DI = dyn_cast<DefInit>(TheInit)) {
    Record *R = DI->getDef();

    // On direct reference to a leaf DagNode (SDNode) or a pattern fragment, create
    // a new InvTreePatternNode.
    if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) {
      return ParseTreePattern(DagInit::get(DI, "", 
          std::vector<std::pair<Init*, std::string> >()), OpName);
    }

    // Treat as an input element
    InvTreePatternNode *Res = new InvTreePatternNode(DI);
    if (R->getName() == "node" && OpName.empty()) {
      error("'node' requires an opname to match operand lists!");
    }

    Res->setName(OpName);
    return Res;
   }

  if (IntInit *II = dyn_cast<IntInit>(TheInit)) {
    if (!OpName.empty()) {
      error("Constant int args should not have a name!");
    }
    return new InvTreePatternNode(II);
  }

  if (BitsInit *BI = dyn_cast<BitsInit>(TheInit)) {
    // Convert to IntInit
    Init *II = BI->convertInitializerTo(IntRecTy::get());
    if (II == 0 || !isa<IntInit>(II)) {
      error("Bits values must be integer constants!");
    }
    return ParseTreePattern(II, OpName);
  }

  DagInit *Dag = dyn_cast<DagInit>(TheInit);
  if (!Dag) {
    TheInit->dump();
    error("The Pattern has an unexpected init type.");
  }
  DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
  if (!OpDef) {
    error("Thye Pattern has an unexpected operator type.");
  }
  Record *OpRec = OpDef->getDef();

  if (OpRec->isSubClassOf("ValueType")) {
    // ValueType is the type of a leaf node.
    if (Dag->getNumArgs() != 1) {
      error("Expected 1 argument for a ValueType operator.");
    }
    InvTreePatternNode *New = ParseTreePattern(Dag->getArg(0), Dag->getArgName(0));

    // assert(New->getNumTypes() == 1 && "Unable to handle multiple types!");
    // New->UpdateNodeType(0, getValueType(OpRec), *this);

    if (!OpName.empty()) {
      error("ValueType should not have a name!");
    }
    return New;
  }

  // Verify that this makes sense for an operator
  if (!OpRec->isSubClassOf("PatFrag") && !OpRec->isSubClassOf("SDNode") &&
    !OpRec->isSubClassOf("Instruction") && !OpRec->isSubClassOf("SDNodeXForm") &&
    !OpRec->isSubClassOf("Intrinsic") && OpRec->getName() != "set" &&
    OpRec->getName() != "implicit" && OpRec->getName() != "outs" &&
    OpRec->getName() != "ins" && OpRec->getName() != "null_frag") {
    error("Unrecognized node '" + OpRec->getName() + "'!");
  }

  // Unlike Regular treepatterns, we assume all patterns are "input" patterns
  // in the TableGen context
  if (OpRec->isSubClassOf("Instruction") ||
    OpRec->isSubClassOf("SDNodeXForm")) {
    error("Cannot use '" + OpRec->getName() + "' in the output pattern.");
  }

  std::vector<InvTreePatternNode*> Children;

  // Parse operands
  for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
    Children.push_back(ParseTreePattern(Dag->getArg(i), Dag->getArgName(i)));
  }

  if (OpRec->isSubClassOf("Intrinsic")) {
    // Unhandled...
    DEBUG(error("Intrinsics unhandled at this time."););

CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
  : TheDef(R), AsmString(AsmStr) {
  Name      = R->getValueAsString("Name");
  Namespace = R->getValueAsString("Namespace");

  isReturn     = R->getValueAsBit("isReturn");
  isBranch     = R->getValueAsBit("isBranch");
  isBarrier    = R->getValueAsBit("isBarrier");
  isCall       = R->getValueAsBit("isCall");
  isLoad       = R->getValueAsBit("isLoad");
  isStore      = R->getValueAsBit("isStore");
  bool isTwoAddress = R->getValueAsBit("isTwoAddress");
  isPredicated = false;   // set below.
  isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
  isCommutable = R->getValueAsBit("isCommutable");
  isTerminator = R->getValueAsBit("isTerminator");
  isReMaterializable = R->getValueAsBit("isReMaterializable");
  hasDelaySlot = R->getValueAsBit("hasDelaySlot");
  usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
  hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
  noResults    = R->getValueAsBit("noResults");
  hasVariableNumberOfOperands = false;
  
  DagInit *DI;
  try {
    DI = R->getValueAsDag("OperandList");
  } catch (...) {
    // Error getting operand list, just ignore it (sparcv9).
    AsmString.clear();
    OperandList.clear();
    return;
  }

  unsigned MIOperandNo = 0;
  std::set<std::string> OperandNames;
  for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
    DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
    if (!Arg)
      throw "Illegal operand for the '" + R->getName() + "' instruction!";

    Record *Rec = Arg->getDef();
    std::string PrintMethod = "printOperand";
    unsigned NumOps = 1;
    DagInit *MIOpInfo = 0;
    if (Rec->isSubClassOf("Operand")) {
      PrintMethod = Rec->getValueAsString("PrintMethod");
      MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
      
      // Verify that MIOpInfo has an 'ops' root value.
      if (!dynamic_cast<DefInit*>(MIOpInfo->getOperator()) ||
          dynamic_cast<DefInit*>(MIOpInfo->getOperator())
               ->getDef()->getName() != "ops")
        throw "Bad value for MIOperandInfo in operand '" + Rec->getName() +
              "'\n";

      // If we have MIOpInfo, then we have #operands equal to number of entries
      // in MIOperandInfo.
      if (unsigned NumArgs = MIOpInfo->getNumArgs())
        NumOps = NumArgs;

      isPredicated |= Rec->isSubClassOf("PredicateOperand");
    } else if (Rec->getName() == "variable_ops") {
      hasVariableNumberOfOperands = true;
      continue;
    } else if (!Rec->isSubClassOf("RegisterClass") && 
               Rec->getName() != "ptr_rc")
      throw "Unknown operand class '" + Rec->getName() +
            "' in instruction '" + R->getName() + "' instruction!";

    // Check that the operand has a name and that it's unique.
    if (DI->getArgName(i).empty())
      throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
        " has no name!";
    if (!OperandNames.insert(DI->getArgName(i)).second)
      throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
        " has the same name as a previous operand!";
    
    OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod, 
                                      MIOperandNo, NumOps, MIOpInfo));
    MIOperandNo += NumOps;
  }

  // Parse Constraints.
  ParseConstraints(R->getValueAsString("Constraints"), this);
  
  // For backward compatibility: isTwoAddress means operand 1 is tied to
  // operand 0.
  if (isTwoAddress) {
    if (!OperandList[1].Constraints[0].empty())
      throw R->getName() + ": cannot use isTwoAddress property: instruction "
            "already has constraint set!";
    OperandList[1].Constraints[0] = "((0 << 16) | (1 << TOI::TIED_TO))";
  }
  
  // Any operands with unset constraints get 0 as their constraint.
  for (unsigned op = 0, e = OperandList.size(); op != e; ++op)
    for (unsigned j = 0, e = OperandList[op].MINumOperands; j != e; ++j)
      if (OperandList[op].Constraints[j].empty())
        OperandList[op].Constraints[j] = "0";
  
//.........这里部分代码省略.........

CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
  AsmString = R->getValueAsString("AsmString");
  Result = R->getValueAsDag("ResultInst");

  // Verify that the root of the result is an instruction.
  DefInit *DI = dynamic_cast<DefInit*>(Result->getOperator());
  if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction"))
    throw TGError(R->getLoc(), "result of inst alias should be an instruction");

  ResultInst = &T.getInstruction(DI->getDef());

  // NameClass - If argument names are repeated, we need to verify they have
  // the same class.
  StringMap<Record*> NameClass;
  for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) {
    DefInit *ADI = dynamic_cast<DefInit*>(Result->getArg(i));
    if (!ADI || Result->getArgName(i).empty())
      continue;
    // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
    // $foo can exist multiple times in the result list, but it must have the
    // same type.
    Record *&Entry = NameClass[Result->getArgName(i)];
    if (Entry && Entry != ADI->getDef())
      throw TGError(R->getLoc(), "result value $" + Result->getArgName(i) +
                    " is both " + Entry->getName() + " and " +
                    ADI->getDef()->getName() + "!");
    Entry = ADI->getDef();
  }

  // Decode and validate the arguments of the result.
  unsigned AliasOpNo = 0;
  for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {

    // Tied registers don't have an entry in the result dag.
    if (ResultInst->Operands[i].getTiedRegister() != -1)
      continue;

    if (AliasOpNo >= Result->getNumArgs())
      throw TGError(R->getLoc(), "not enough arguments for instruction!");

    Record *InstOpRec = ResultInst->Operands[i].Rec;
    unsigned NumSubOps = ResultInst->Operands[i].MINumOperands;
    ResultOperand ResOp(static_cast<int64_t>(0));
    if (tryAliasOpMatch(Result, AliasOpNo, InstOpRec, (NumSubOps > 1),
                        R->getLoc(), T, ResOp)) {
      ResultOperands.push_back(ResOp);
      ResultInstOperandIndex.push_back(std::make_pair(i, -1));
      ++AliasOpNo;
      continue;
    }

    // If the argument did not match the instruction operand, and the operand
    // is composed of multiple suboperands, try matching the suboperands.
    if (NumSubOps > 1) {
      DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
      for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
        if (AliasOpNo >= Result->getNumArgs())
          throw TGError(R->getLoc(), "not enough arguments for instruction!");
        Record *SubRec = dynamic_cast<DefInit*>(MIOI->getArg(SubOp))->getDef();
        if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false,
                            R->getLoc(), T, ResOp)) {
          ResultOperands.push_back(ResOp);
          ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
          ++AliasOpNo;
        } else {
          throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                        " does not match instruction operand class " +
                        (SubOp == 0 ? InstOpRec->getName() :SubRec->getName()));
        }
      }
      continue;
    }
    throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
                  " does not match instruction operand class " +
                  InstOpRec->getName());
  }

  if (AliasOpNo != Result->getNumArgs())
    throw TGError(R->getLoc(), "too many operands for instruction!");
}

CodeGenInstAlias::CodeGenInstAlias(Record *R, unsigned Variant,
                                   CodeGenTarget &T)
    : TheDef(R) {
    Result = R->getValueAsDag("ResultInst");
    AsmString = R->getValueAsString("AsmString");
    AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);


    // Verify that the root of the result is an instruction.
    DefInit *DI = dyn_cast<DefInit>(Result->getOperator());
    if (!DI || !DI->getDef()->isSubClassOf("Instruction"))
        PrintFatalError(R->getLoc(),
                        "result of inst alias should be an instruction");

    ResultInst = &T.getInstruction(DI->getDef());

    // NameClass - If argument names are repeated, we need to verify they have
    // the same class.
    StringMap<Record*> NameClass;
    for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) {
        DefInit *ADI = dyn_cast<DefInit>(Result->getArg(i));
        if (!ADI || Result->getArgName(i).empty())
            continue;
        // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
        // $foo can exist multiple times in the result list, but it must have the
        // same type.
        Record *&Entry = NameClass[Result->getArgName(i)];
        if (Entry && Entry != ADI->getDef())
            PrintFatalError(R->getLoc(), "result value $" + Result->getArgName(i) +
                            " is both " + Entry->getName() + " and " +
                            ADI->getDef()->getName() + "!");
        Entry = ADI->getDef();
    }

    // Decode and validate the arguments of the result.
    unsigned AliasOpNo = 0;
    for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {

        // Tied registers don't have an entry in the result dag unless they're part
        // of a complex operand, in which case we include them anyways, as we
        // don't have any other way to specify the whole operand.
        if (ResultInst->Operands[i].MINumOperands == 1 &&
                ResultInst->Operands[i].getTiedRegister() != -1)
            continue;

        if (AliasOpNo >= Result->getNumArgs())
            PrintFatalError(R->getLoc(), "not enough arguments for instruction!");

        Record *InstOpRec = ResultInst->Operands[i].Rec;
        unsigned NumSubOps = ResultInst->Operands[i].MINumOperands;
        ResultOperand ResOp(static_cast<int64_t>(0));
        if (tryAliasOpMatch(Result, AliasOpNo, InstOpRec, (NumSubOps > 1),
                            R->getLoc(), T, ResOp)) {
            // If this is a simple operand, or a complex operand with a custom match
            // class, then we can match is verbatim.
            if (NumSubOps == 1 ||
                    (InstOpRec->getValue("ParserMatchClass") &&
                     InstOpRec->getValueAsDef("ParserMatchClass")
                     ->getValueAsString("Name") != "Imm")) {
                ResultOperands.push_back(ResOp);
                ResultInstOperandIndex.push_back(std::make_pair(i, -1));
                ++AliasOpNo;

                // Otherwise, we need to match each of the suboperands individually.
            } else {
                DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
                for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
                    Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();

                    // Take care to instantiate each of the suboperands with the correct
                    // nomenclature: $foo.bar
                    ResultOperands.push_back(
                        ResultOperand(Result->getArgName(AliasOpNo) + "." +
                                      MIOI->getArgName(SubOp), SubRec));
                    ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
                }
                ++AliasOpNo;
            }
            continue;
        }

        // If the argument did not match the instruction operand, and the operand
        // is composed of multiple suboperands, try matching the suboperands.
        if (NumSubOps > 1) {
            DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
            for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
                if (AliasOpNo >= Result->getNumArgs())
                    PrintFatalError(R->getLoc(), "not enough arguments for instruction!");
                Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();
                if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false,
                                    R->getLoc(), T, ResOp)) {
                    ResultOperands.push_back(ResOp);
                    ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
                    ++AliasOpNo;
                } else {
                    PrintFatalError(R->getLoc(), "result argument #" + Twine(AliasOpNo) +
                                    " does not match instruction operand class " +
                                    (SubOp == 0 ? InstOpRec->getName() :SubRec->getName()));
                }
            }
//.........这里部分代码省略.........

//.........这里部分代码省略.........
        // Print out the pattern that matched...
        DEBUG(OS << "    std::cerr << \"  " << P->getRecord()->getName() <<'"');
        DEBUG(for (unsigned i = 0, e = Operands.size(); i != e; ++i)
                if (Operands[i].first->isLeaf()) {
                  Record *RV = Operands[i].first->getValueRecord();
                  assert(RV->isSubClassOf("RegisterClass") &&
                         "Only handles registers here so far!");
                  OS << " << \" %reg\" << " << Operands[i].second
                     << "->Val";
                } else {
                  OS << " << ' ' << " << Operands[i].second
                     << "->Val";
                });
        DEBUG(OS << " << \"\\n\";\n");
        
        // Generate the reduction code appropriate to the particular type of
        // pattern that this is...
        switch (P->getPatternType()) {
        case Pattern::Instruction:
          // Instruction patterns just emit a single MachineInstr, using BuildMI
          OS << "    BuildMI(MBB, " << Target.getName() << "::"
             << P->getRecord()->getName() << ", " << Operands.size();
          if (P->getResult()) OS << ", NewReg";
          OS << ")";

          for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
            TreePatternNode *Op = Operands[i].first;
            if (Op->isLeaf()) {
              Record *RV = Op->getValueRecord();
              assert(RV->isSubClassOf("RegisterClass") &&
                     "Only handles registers here so far!");
              OS << ".addReg(" << Operands[i].second << "->Val)";
            } else if (Op->getOperator()->getName() == "imm") {
              OS << ".addZImm(" << Operands[i].second << "->Val)";
            } else if (Op->getOperator()->getName() == "basicblock") {
              OS << ".addMBB(" << Operands[i].second << "->Val)";
            } else {
              assert(0 && "Unknown value type!");
            }
          }
          OS << ";\n";
          break;
        case Pattern::Expander: {
          // Expander patterns emit one machine instr for each instruction in
          // the list of instructions expanded to.
          ListInit *Insts = P->getRecord()->getValueAsListInit("Result");
          for (unsigned IN = 0, e = Insts->getSize(); IN != e; ++IN) {
            DagInit *DIInst = dynamic_cast<DagInit*>(Insts->getElement(IN));
            if (!DIInst) P->error("Result list must contain instructions!");
            Record *InstRec  = DIInst->getNodeType();
            Pattern *InstPat = getPattern(InstRec);
            if (!InstPat || InstPat->getPatternType() != Pattern::Instruction)
              P->error("Instruction list must contain Instruction patterns!");
            
            bool hasResult = InstPat->getResult() != 0;
            if (InstPat->getNumArgs() != DIInst->getNumArgs()-hasResult) {
              P->error("Incorrect number of arguments specified for inst '" +
                       InstPat->getRecord()->getName() + "' in result list!");
            }

            // Start emission of the instruction...
            OS << "    BuildMI(MBB, " << Target.getName() << "::"
               << InstRec->getName() << ", "
               << DIInst->getNumArgs()-hasResult;
            // Emit register result if necessary..
            if (hasResult) {
              std::string ArgNameVal =
                getArgName(P, DIInst->getArgName(0), Operands);
              PrintExpanderOperand(DIInst->getArg(0), ArgNameVal,
                                   InstPat->getResultNode(), P, false,
                                   OS << ", ");
            }
            OS << ")";

            for (unsigned i = hasResult, e = DIInst->getNumArgs(); i != e; ++i){
              std::string ArgNameVal =
                getArgName(P, DIInst->getArgName(i), Operands);

              PrintExpanderOperand(DIInst->getArg(i), ArgNameVal,
                                   InstPat->getArg(i-hasResult), P, true, OS);
            }

            OS << ";\n";
          }
          break;
        }
        default:
          assert(0 && "Reduction of this type of pattern not implemented!");
        }

        OS << "    Val = new ReducedValue_" << SlotName << "(" << Result<<");\n"
           << "    break;\n"
           << "  }\n";
      }
    
    
    OS << "  default: assert(0 && \"Unknown " << SlotName << " pattern!\");\n"
       << "  }\n\n  N->addValue(Val);  // Do not ever recalculate this\n"
       << "  return Val;\n}\n\n";
  }

/// tryAliasOpMatch - This is a helper function for the CodeGenInstAlias
/// constructor.  It checks if an argument in an InstAlias pattern matches
/// the corresponding operand of the instruction.  It returns true on a
/// successful match, with ResOp set to the result operand to be used.
bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
                                       Record *InstOpRec, bool hasSubOps,
                                       ArrayRef<SMLoc> Loc, CodeGenTarget &T,
                                       ResultOperand &ResOp) {
    Init *Arg = Result->getArg(AliasOpNo);
    DefInit *ADI = dyn_cast<DefInit>(Arg);
    Record *ResultRecord = ADI ? ADI->getDef() : nullptr;

    if (ADI && ADI->getDef() == InstOpRec) {
        // If the operand is a record, it must have a name, and the record type
        // must match up with the instruction's argument type.
        if (Result->getArgName(AliasOpNo).empty())
            PrintFatalError(Loc, "result argument #" + Twine(AliasOpNo) +
                            " must have a name!");
        ResOp = ResultOperand(Result->getArgName(AliasOpNo), ResultRecord);
        return true;
    }

    // For register operands, the source register class can be a subclass
    // of the instruction register class, not just an exact match.
    if (InstOpRec->isSubClassOf("RegisterOperand"))
        InstOpRec = InstOpRec->getValueAsDef("RegClass");

    if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand"))
        ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit();

    if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
        if (!InstOpRec->isSubClassOf("RegisterClass"))
            return false;
        if (!T.getRegisterClass(InstOpRec)
                .hasSubClass(&T.getRegisterClass(ADI->getDef())))
            return false;
        ResOp = ResultOperand(Result->getArgName(AliasOpNo), ResultRecord);
        return true;
    }

    // Handle explicit registers.
    if (ADI && ADI->getDef()->isSubClassOf("Register")) {
        if (InstOpRec->isSubClassOf("OptionalDefOperand")) {
            DagInit *DI = InstOpRec->getValueAsDag("MIOperandInfo");
            // The operand info should only have a single (register) entry. We
            // want the register class of it.
            InstOpRec = cast<DefInit>(DI->getArg(0))->getDef();
        }

        if (!InstOpRec->isSubClassOf("RegisterClass"))
            return false;

        if (!T.getRegisterClass(InstOpRec)
                .contains(T.getRegBank().getReg(ADI->getDef())))
            PrintFatalError(Loc, "fixed register " + ADI->getDef()->getName() +
                            " is not a member of the " + InstOpRec->getName() +
                            " register class!");

        if (!Result->getArgName(AliasOpNo).empty())
            PrintFatalError(Loc, "result fixed register argument must "
                            "not have a name!");

        ResOp = ResultOperand(ResultRecord);
        return true;
    }

    // Handle "zero_reg" for optional def operands.
    if (ADI && ADI->getDef()->getName() == "zero_reg") {

        // Check if this is an optional def.
        // Tied operands where the source is a sub-operand of a complex operand
        // need to represent both operands in the alias destination instruction.
        // Allow zero_reg for the tied portion. This can and should go away once
        // the MC representation of things doesn't use tied operands at all.
        //if (!InstOpRec->isSubClassOf("OptionalDefOperand"))
        //  throw TGError(Loc, "reg0 used for result that is not an "
        //                "OptionalDefOperand!");

        ResOp = ResultOperand(static_cast<Record*>(nullptr));
        return true;
    }

    // Literal integers.
    if (IntInit *II = dyn_cast<IntInit>(Arg)) {
        if (hasSubOps || !InstOpRec->isSubClassOf("Operand"))
            return false;
        // Integer arguments can't have names.
        if (!Result->getArgName(AliasOpNo).empty())
            PrintFatalError(Loc, "result argument #" + Twine(AliasOpNo) +
                            " must not have a name!");
        ResOp = ResultOperand(II->getValue());
        return true;
    }

    // If both are Operands with the same MVT, allow the conversion. It's
    // up to the user to make sure the values are appropriate, just like
    // for isel Pat's.
    if (InstOpRec->isSubClassOf("Operand") &&
            ADI->getDef()->isSubClassOf("Operand")) {
        // FIXME: What other attributes should we check here? Identical
//.........这里部分代码省略.........

void MatcherGen::
EmitResultInstructionAsOperand(const TreePatternNode *N,
                               SmallVectorImpl<unsigned> &OutputOps) {
  Record *Op = N->getOperator();
  const CodeGenTarget &CGT = CGP.getTargetInfo();
  CodeGenInstruction &II = CGT.getInstruction(Op);
  const DAGInstruction &Inst = CGP.getInstruction(Op);

  bool isRoot = N == Pattern.getDstPattern();

  // TreeHasOutGlue - True if this tree has glue.
  bool TreeHasInGlue = false, TreeHasOutGlue = false;
  if (isRoot) {
    const TreePatternNode *SrcPat = Pattern.getSrcPattern();
    TreeHasInGlue = SrcPat->TreeHasProperty(SDNPOptInGlue, CGP) ||
                    SrcPat->TreeHasProperty(SDNPInGlue, CGP);

    // FIXME2: this is checking the entire pattern, not just the node in
    // question, doing this just for the root seems like a total hack.
    TreeHasOutGlue = SrcPat->TreeHasProperty(SDNPOutGlue, CGP);
  }

  // NumResults - This is the number of results produced by the instruction in
  // the "outs" list.
  unsigned NumResults = Inst.getNumResults();

  // Number of operands we know the output instruction must have. If it is
  // variadic, we could have more operands.
  unsigned NumFixedOperands = II.Operands.size();

  SmallVector<unsigned, 8> InstOps;

  // Loop over all of the fixed operands of the instruction pattern, emitting
  // code to fill them all in. The node 'N' usually has number children equal to
  // the number of input operands of the instruction.  However, in cases where
  // there are predicate operands for an instruction, we need to fill in the
  // 'execute always' values. Match up the node operands to the instruction
  // operands to do this.
  unsigned ChildNo = 0;
  for (unsigned InstOpNo = NumResults, e = NumFixedOperands;
       InstOpNo != e; ++InstOpNo) {
    // Determine what to emit for this operand.
    Record *OperandNode = II.Operands[InstOpNo].Rec;
    if (OperandNode->isSubClassOf("OperandWithDefaultOps") &&
        !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
      // This is a predicate or optional def operand; emit the
      // 'default ops' operands.
      const DAGDefaultOperand &DefaultOp
        = CGP.getDefaultOperand(OperandNode);
      for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
        EmitResultOperand(DefaultOp.DefaultOps[i].get(), InstOps);
      continue;
    }

    // Otherwise this is a normal operand or a predicate operand without
    // 'execute always'; emit it.

    // For operands with multiple sub-operands we may need to emit
    // multiple child patterns to cover them all.  However, ComplexPattern
    // children may themselves emit multiple MI operands.
    unsigned NumSubOps = 1;
    if (OperandNode->isSubClassOf("Operand")) {
      DagInit *MIOpInfo = OperandNode->getValueAsDag("MIOperandInfo");
      if (unsigned NumArgs = MIOpInfo->getNumArgs())
        NumSubOps = NumArgs;
    }

    unsigned FinalNumOps = InstOps.size() + NumSubOps;
    while (InstOps.size() < FinalNumOps) {
      const TreePatternNode *Child = N->getChild(ChildNo);
      unsigned BeforeAddingNumOps = InstOps.size();
      EmitResultOperand(Child, InstOps);
      assert(InstOps.size() > BeforeAddingNumOps && "Didn't add any operands");

      // If the operand is an instruction and it produced multiple results, just
      // take the first one.
      if (!Child->isLeaf() && Child->getOperator()->isSubClassOf("Instruction"))
        InstOps.resize(BeforeAddingNumOps+1);

      ++ChildNo;
    }
  }

  // If this is a variadic output instruction (i.e. REG_SEQUENCE), we can't
  // expand suboperands, use default operands, or other features determined from
  // the CodeGenInstruction after the fixed operands, which were handled
  // above. Emit the remaining instructions implicitly added by the use for
  // variable_ops.
  if (II.Operands.isVariadic) {
    for (unsigned I = ChildNo, E = N->getNumChildren(); I < E; ++I)
      EmitResultOperand(N->getChild(I), InstOps);
  }

  // If this node has input glue or explicitly specified input physregs, we
  // need to add chained and glued copyfromreg nodes and materialize the glue
  // input.
  if (isRoot && !PhysRegInputs.empty()) {
    // Emit all of the CopyToReg nodes for the input physical registers.  These
    // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
    for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
//.........这里部分代码省略.........

static bool populateInstruction(const CodeGenInstruction &CGI,
                                unsigned Opc,
                      std::map<unsigned, std::vector<OperandInfo> >& Operands){
  const Record &Def = *CGI.TheDef;
  // If all the bit positions are not specified; do not decode this instruction.
  // We are bound to fail!  For proper disassembly, the well-known encoding bits
  // of the instruction must be fully specified.
  //
  // This also removes pseudo instructions from considerations of disassembly,
  // which is a better design and less fragile than the name matchings.
  // Ignore "asm parser only" instructions.
  if (Def.getValueAsBit("isAsmParserOnly") ||
      Def.getValueAsBit("isCodeGenOnly"))
    return false;

  BitsInit &Bits = getBitsField(Def, "Inst");
  if (Bits.allInComplete()) return false;

  std::vector<OperandInfo> InsnOperands;

  // If the instruction has specified a custom decoding hook, use that instead
  // of trying to auto-generate the decoder.
  std::string InstDecoder = Def.getValueAsString("DecoderMethod");
  if (InstDecoder != "") {
    InsnOperands.push_back(OperandInfo(InstDecoder));
    Operands[Opc] = InsnOperands;
    return true;
  }

  // Generate a description of the operand of the instruction that we know
  // how to decode automatically.
  // FIXME: We'll need to have a way to manually override this as needed.

  // Gather the outputs/inputs of the instruction, so we can find their
  // positions in the encoding.  This assumes for now that they appear in the
  // MCInst in the order that they're listed.
  std::vector<std::pair<Init*, std::string> > InOutOperands;
  DagInit *Out  = Def.getValueAsDag("OutOperandList");
  DagInit *In  = Def.getValueAsDag("InOperandList");
  for (unsigned i = 0; i < Out->getNumArgs(); ++i)
    InOutOperands.push_back(std::make_pair(Out->getArg(i), Out->getArgName(i)));
  for (unsigned i = 0; i < In->getNumArgs(); ++i)
    InOutOperands.push_back(std::make_pair(In->getArg(i), In->getArgName(i)));

  // Search for tied operands, so that we can correctly instantiate
  // operands that are not explicitly represented in the encoding.
  std::map<std::string, std::string> TiedNames;
  for (unsigned i = 0; i < CGI.Operands.size(); ++i) {
    int tiedTo = CGI.Operands[i].getTiedRegister();
    if (tiedTo != -1) {
      TiedNames[InOutOperands[i].second] = InOutOperands[tiedTo].second;
      TiedNames[InOutOperands[tiedTo].second] = InOutOperands[i].second;
    }
  }

  // For each operand, see if we can figure out where it is encoded.
  for (std::vector<std::pair<Init*, std::string> >::iterator
       NI = InOutOperands.begin(), NE = InOutOperands.end(); NI != NE; ++NI) {
    std::string Decoder = "";

    // At this point, we can locate the field, but we need to know how to
    // interpret it.  As a first step, require the target to provide callbacks
    // for decoding register classes.
    // FIXME: This need to be extended to handle instructions with custom
    // decoder methods, and operands with (simple) MIOperandInfo's.
    TypedInit *TI = dynamic_cast<TypedInit*>(NI->first);
    RecordRecTy *Type = dynamic_cast<RecordRecTy*>(TI->getType());
    Record *TypeRecord = Type->getRecord();
    bool isReg = false;
    if (TypeRecord->isSubClassOf("RegisterOperand"))
      TypeRecord = TypeRecord->getValueAsDef("RegClass");
    if (TypeRecord->isSubClassOf("RegisterClass")) {
      Decoder = "Decode" + TypeRecord->getName() + "RegisterClass";
      isReg = true;
    }

    RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod");
    StringInit *String = DecoderString ?
      dynamic_cast<StringInit*>(DecoderString->getValue()) : 0;
    if (!isReg && String && String->getValue() != "")
      Decoder = String->getValue();

    OperandInfo OpInfo(Decoder);
    unsigned Base = ~0U;
    unsigned Width = 0;
    unsigned Offset = 0;

    for (unsigned bi = 0; bi < Bits.getNumBits(); ++bi) {
      VarInit *Var = 0;
      VarBitInit *BI = dynamic_cast<VarBitInit*>(Bits.getBit(bi));
      if (BI)
        Var = dynamic_cast<VarInit*>(BI->getVariable());
      else
        Var = dynamic_cast<VarInit*>(Bits.getBit(bi));

      if (!Var) {
        if (Base != ~0U) {
          OpInfo.addField(Base, Width, Offset);
          Base = ~0U;
          Width = 0;
//.........这里部分代码省略.........

CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
  : TheDef(R), Name(R->getName()), EnumValue(-1) {
  // Rename anonymous register classes.
  if (R->getName().size() > 9 && R->getName()[9] == '.') {
    static unsigned AnonCounter = 0;
    R->setName("AnonRegClass_"+utostr(AnonCounter++));
  }

  std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
  for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
    Record *Type = TypeList[i];
    if (!Type->isSubClassOf("ValueType"))
      throw "RegTypes list member '" + Type->getName() +
        "' does not derive from the ValueType class!";
    VTs.push_back(getValueType(Type));
  }
  assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");

  // Allocation order 0 is the full set. AltOrders provides others.
  const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
  ListInit *AltOrders = R->getValueAsListInit("AltOrders");
  Orders.resize(1 + AltOrders->size());

  // Default allocation order always contains all registers.
  for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
    Orders[0].push_back((*Elements)[i]);
    Members.insert(RegBank.getReg((*Elements)[i]));
  }

  // Alternative allocation orders may be subsets.
  SetTheory::RecSet Order;
  for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
    RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
    Orders[1 + i].append(Order.begin(), Order.end());
    // Verify that all altorder members are regclass members.
    while (!Order.empty()) {
      CodeGenRegister *Reg = RegBank.getReg(Order.back());
      Order.pop_back();
      if (!contains(Reg))
        throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
                      " is not a class member");
    }
  }

  // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
  ListInit *SRC = R->getValueAsListInit("SubRegClasses");
  for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
    DagInit *DAG = dynamic_cast<DagInit*>(*i);
    if (!DAG) throw "SubRegClasses must contain DAGs";
    DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
    Record *RCRec;
    if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
      throw "Operator '" + DAG->getOperator()->getAsString() +
        "' in SubRegClasses is not a RegisterClass";
    // Iterate over args, all SubRegIndex instances.
    for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
         ai != ae; ++ai) {
      DefInit *Idx = dynamic_cast<DefInit*>(*ai);
      Record *IdxRec;
      if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
        throw "Argument '" + (*ai)->getAsString() +
          "' in SubRegClasses is not a SubRegIndex";
      if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
        throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
    }
  }

  // Allow targets to override the size in bits of the RegisterClass.
  unsigned Size = R->getValueAsInt("Size");

  Namespace = R->getValueAsString("Namespace");
  SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
  SpillAlignment = R->getValueAsInt("Alignment");
  CopyCost = R->getValueAsInt("CopyCost");
  Allocatable = R->getValueAsBit("isAllocatable");
  AltOrderSelect = R->getValueAsCode("AltOrderSelect");
}