C++ xHWREG函数代码示例

//*****************************************************************************
//
//! !brief xrtc 001 test for clock config.
//!
//! \return None.
//
//*****************************************************************************
static void xrtc001Execute_clock_Config(void)
{
		xSysCtlPeripheralEnable(SYSCTL_PERIPH_PWR);
		SysCtlBackupAccessEnable();
	
		SysCtlLSEConfig(SYSCTL_LSE_OSC_EN);		
		TestAssert((xHWREG(RCC_BDCR)&0x03) == 0x03, "enable LSE error!");
	
		SysCtlPeripheralClockSourceSet(SYSCTL_RTC_LSE); 
		TestAssert(xHWREG(RCC_BDCR)&((SYSCTL_RTC_LSE&0x03)<<8) == ((SYSCTL_RTC_LSE&0x03)<<8), "select LSE as RTC clock error!");
		
		xSysCtlPeripheralEnable(SYSCTL_PERIPH_RTC);
		TestAssert((xHWREG(RCC_BDCR)&0x8000) == 0x8000, "enable RTC clock error!");
}

//*****************************************************************************
//
//! \brief Sets the control parameters for a DMA channel.
//!
//! \param ulChannelID is the DMA channel ID.
//! \param ulControl is logical OR of several control values to set the control
//! parameters for the channel.
//!
//! This function is used to set control parameters for a uDMA transfer.  These
//! are typically parameters that are not changed often.
//!
//! The \e ulControl parameter is the logical OR of five values: the data size,
//! the source address increment, the destination address increment.
//!
//! Choose the source data size from one of \b PDMA_WIDTH_8BIT, 
//! \b PDMA_WIDTH_16BIT,  \b or PDMA_WIDTH_32BIT to select a data size 
//! of 8, 16, or 32 bits.
//!
//! Choose the destination data size from one of \b PDMA_WIDTH_8BIT, 
//! \b PDMA_WIDTH_16BIT,  \b or PDMA_WIDTH_32BIT to select a data size 
//! of 8, 16, or 32 bits.
//!
//! Choose the source address increment from one of \b PDMA_SRC_DIR_INC,
//! \b PDMA_SRC_DIR_FIXED to selectan address increment or  select 
//! non-incrementing 
//!
//! Choose the destination address increment from one of \b PDMA_DST_DIR_INC,
//! \b PDMA_DST_DIR_FIXED to selectan address increment or  select 
//! non-incrementing 
//!
//! \note The address increment cannot be smaller than the data size. 
//! The transfer may use burst or single.
//!
//! \return None.
//
//*****************************************************************************
void
PDMAChannelControlSet(unsigned long ulChannelID,
                      unsigned long ulControl)
{
    
    xASSERT(xDMAChannelIDValid(ulChannelID));


    xHWREG(g_psDMAChannelAddress[ulChannelID] + PDMA_CSR) &= 
    ~(PDMA_CSR_SDA_M | PDMA_CSR_DAD_M | PDMA_CSR_TWS_M);
    
    xHWREG(g_psDMAChannelAddress[ulChannelID] + PDMA_CSR) |= ulControl;
   
}

//*****************************************************************************
//
//! \brief Cancellation of ACMP peripheral that will decrease the offset 
//! between CP and CN.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulInputRef Specify the CMP_OP reference input for cancellation. 
//!
//! This function Cancellation of ACMP peripheral that will decrease the offset 
//! between CP and CN.  
//!
//! \return None.
//
//*****************************************************************************
void
ACMPCancellation(unsigned long ulBase,  unsigned long ulCompID,
                 unsigned long ulInputRef)
{	
    unsigned long i=0,ulTemp=0,ulTemp1=0;
    xASSERT(ulBase == ACMP_BASE);
    xASSERT((ulCompID >= 0) && (ulCompID < 2));
    
    ulTemp1 = xHWREG(ulBase + ACMP_OPACR + ulCompID*0x100);
    xHWREG(ulBase + ACMP_IER + ulCompID*0x100) = 0;
    xHWREG(ulBase + ACMP_ICLR + ulCompID*0x100) = 3;
    xHWREG(ulBase + ACMP_OPACR + ulCompID*0x100) = ACMP_OPACR_EN | 
                                                   ACMP_OPACR_AOFM | 
                                                   ulInputRef;

    xHWREG(ulBase + ACMP_OFVCR + ulCompID*0x100) = 0;
    while (ulTemp ==0)
    {
        xHWREG(ulBase + ACMP_OFVCR + ulCompID*0x100) = i;
        SysCtlDelay(20000);
        ulTemp = (xHWREG(ulBase + ACMP_OPACR + ulCompID*0x100)
                  & ACMP_OPACR_CMPS);
        i++;
    if(i >64){ulTemp = 1;} 
    }

    xHWREG(ulBase + ACMP_OPACR + ulCompID*0x100) = ulTemp1;
    
    return ;
}

//*****************************************************************************
//
//! \brief xsysctl 005 test of Brown-Out Detector Control Register test .
//!
//! \return None.
//
//*****************************************************************************
static void xsysctl_Bod_test(void)
{
    xtBoolean xtTemp;
    unsigned long ulTemp,i; 
    
    SysCtlBODEnable(xtrue);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((GCR_BODCR_BOD_EN == (ulTemp & GCR_BODCR_BOD_EN)),
                                                        "xsysctl API error!");
 
    SysCtlBODEnable(xfalse);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((0 == (ulTemp & GCR_BODCR_BOD_EN)), "xsysctl API error!");
    //
    // Set Threshold Voltage as 2.2V test
    //
    for(i = 0; i < 4; i++)
    {
        SysCtlBODVoltSelect(ulBodVoltage[i]);
        ulTemp = xHWREG(GCR_BODCR);
        TestAssert((i == (ulTemp & GCR_BODCR_BOD_VL_M)>>GCR_BODCR_BOD_VL_S),
                                                          "xsysctl API error!");
    }
    
    SysCtlBODLowPowerModeEnable(xtrue);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((GCR_BODCR_BOD_LPM == (ulTemp & GCR_BODCR_BOD_LPM)),
                                                          "xsysctl API error!");
    
    SysCtlBODLowPowerModeEnable(xfalse);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((0 == (ulTemp & GCR_BODCR_BOD_LPM)), "xsysctl API error!");
    
    SysCtlLowVoltRstEnable(xtrue);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((GCR_BODCR_LVR_EN == (ulTemp & GCR_BODCR_LVR_EN)),
                                                          "xsysctl API error!");
    
    SysCtlLowVoltRstEnable(xfalse);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((0 == (ulTemp & GCR_BODCR_LVR_EN)), "xsysctl API error!");
    
    xtTemp = SysCtlBODStateGet();
    TestAssert((xtTemp==0 ),"xsysctl API \"SysCtlBODStateGet()\" error!");
    
    SysCtlBODRstEnable(xtrue);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((GCR_BODCR_BOD_RSTEN == (ulTemp & GCR_BODCR_BOD_RSTEN)),
                                                          "xsysctl API error!");
    
    SysCtlBODRstEnable(xfalse);
    ulTemp = xHWREG(GCR_BODCR);
    TestAssert((0 == (ulTemp & GCR_BODCR_BOD_RSTEN)),"xsysctl API error!");
}

//*****************************************************************************
//
//! \brief xrtc001 test main body for rtc initialization.
//!
//! \return None.
//
//*****************************************************************************
static void xrtc001Execute_Init()
{
		unsigned long rtcprevload=0;
		xrtc001Execute_clock_Config();
    //
    // RTC initialization.
    // 		
		RTCTimeInit(0x7fff);
		TestAssert(1==RTCTimeInit(0x7fff) ,
		  "xrtc API \"RTCTimeInit\" error!");
		rtcprevload = xHWREG(RTC_PRLH);
		rtcprevload <<= 16;
		rtcprevload |= xHWREG(RTC_PRLL);
		TestAssert(rtcprevload == 0x7FFF, "RTC Prevload value init error!");	
}

//*****************************************************************************
//
//! \brief Set Watchdog Timer Prescaler.
//!
//! \param ulDivide is the peripheral clock divide to be set.
//!
//! Set Watchdog Timer Prescaler.
//!
//! \return None.
//
//*****************************************************************************
void
WDTimerPrescalerSet(unsigned long ulDivide)
{
    //
    // Check the arguments.
    //
    xASSERT((ulDivide == WDT_PRESCALER_1) ||
            (ulDivide == WDT_PRESCALER_2) ||
            (ulDivide == WDT_PRESCALER_4) ||
            (ulDivide == WDT_PRESCALER_8));


    xHWREG(WWDG_CFR) &= ~WWDG_CFR_WDGTB_M;
    xHWREG(WWDG_CFR) |= ulDivide;
}

//*****************************************************************************
//
//! \brief xsysctl 001 test of HCLK Source Set test .
//!
//! \return None.
//
//*****************************************************************************
static void xsysctl_SysCtlHClockSourceSet_test(void)
{
    unsigned long ulTemp,i;
    
    for(i = 0; i < 3; i++)
    {
        SysCtlHClockSourceSet(ulHCLKSource[i]);
        ulTemp = xHWREG(SYSCLK_CLKSEL0);
        TestAssert((ulHCLKRegister[i] == (ulTemp & SYSCLK_CLKSEL0_HCLK_M)),"xsysctl API error!");
    }

    SysCtlHClockSourceSet(SYSCTL_HLCK_S_INT22M);
    ulTemp = xHWREG(SYSCLK_CLKSEL0);
    TestAssert((7 == (ulTemp & SYSCLK_CLKSEL0_HCLK_M)),"xsysctl API error!");
}

//*****************************************************************************
//
//! \brief Sets the control parameters for a DMA channel.
//!
//! \param ulChannelID is the DMA channel ID.
//! \param ulControl is logical OR of several control values to set the control
//! parameters for the channel.
//!
//! This function is used to set control parameters for a uDMA transfer.  These
//! are typically parameters that are not changed often.
//!
//! The \e ulControl parameter is the logical OR of five values: the data size
//! of Memory, the data size of Peripheral, the Circular mode enable or not,
//! the Memory address increment, the Peripheral address increment.
//!
//! Choose the source data size of Memory from one of \b DMA_MEM_WIDTH_8BIT, 
//! \b DMA_MEM_WIDTH_16BIT,  \b or DMA_MEM_WIDTH_32BIT to select a data size 
//! of 8, 16, or 32 bits.
//!
//! Choose the source data size of Peripheral from one of \b DMA_PER_WIDTH_8BIT, 
//! \b DMA_PER_WIDTH_16BIT,  \b or DMA_PER_WIDTH_32BIT to select a data size 
//! of 8, 16, or 32 bits.
//!
//! Choose the destination data size from one of \b DMA_WIDTH_8BIT, 
//! \b DMA_WIDTH_16BIT,  \b or DMA_WIDTH_32BIT to select a data size 
//! of 8, 16, or 32 bits.
//!
//! Choose the Memory address increment from one of \b DMA_MEM_DIR_INC,
//! \b DMA_MEM_DIR_FIXED to selectan address increment or  select 
//! non-incrementing.
//!
//! Choose the Peripheral address increment from one of \b DMA_PER_DIR_INC,
//! \b DMA_PER_DIR_FIXED to selectan address increment or  select 
//! non-incrementing .
//!
//! Choose the the Circular mode from one of \b DMA_MODE_CIRC_EN,
//! \b DMA_MODE_CIRC_DIS to Enable circular mode or  disable 
//! circular mode.
//!
//! \note The address increment cannot be smaller than the data size. 
//! The transfer may use burst or single.
//!
//! \return None.
//
//*****************************************************************************
void
DMAChannelControlSet(unsigned long ulChannelID,
                      unsigned long ulControl)
{
    
    xASSERT(xDMAChannelIDValid(ulChannelID));


    xHWREG(g_psDMAChannel[ulChannelID]) &= 
    ~(DMA_CCR1_MSIZE_M | DMA_CCR1_PSIZE_M | DMA_CCR1_MINC |
      DMA_CCR1_PINC);
    
    xHWREG(g_psDMAChannel[ulChannelID]) |= ulControl;
   
}

//*****************************************************************************
//
//! \brief Enable the Watchdog timer.
//!
//! \param None.
//!
//! This function is to Enable the Watchdog timer.
//!
//! \note When use watch dog WDTimerEnable() should be called after call 
//! WDTimerInit(ulConfig).
//!
//! \return None.
//
//*****************************************************************************
void 
WDTimerEnable(void)
{   
    SysCtlKeyAddrUnlock();
    xHWREG(WDT_WTCR) |= WDT_WTCR_WTE;
    SysCtlKeyAddrLock();
}

static void I2CStopSend (unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    xASSERT((ulBase == I2C0_BASE) || (ulBase == I2C1_BASE));

    if (xHWREG(ulBase + I2C_O_CON) & I2C_CON_STA)
    {
        xHWREG(ulBase + I2C_O_CON) &= ~I2C_CON_STA;
    }
	xHWREG(ulBase + I2C_O_CON) |= I2C_CON_STO;
    xHWREG(ulBase + I2C_O_CON) |= I2C_CON_SI;

	xHWREG(ulBase + I2C_O_CON) &= ~I2C_CON_AA;
}

//*****************************************************************************
//
//! \brief xsysctl 002 test of SysCtl Power Down Enable test .
//!
//! \return None.
//
//*****************************************************************************
static void xsysctl_SysCtlPowerDownEnable_test(void)
{
    unsigned long ulTemp;
    SysCtlPowerDownEnable(xtrue);
    ulTemp = xHWREG(SYSCLK_PWRCON);
    TestAssert(ulTemp == 0x0000009D, "xsysctl API  error!");
}

//*****************************************************************************
//
//! \brief Restart the Watchdog timer. 
//!
//! \param None.
//!
//! This function is to restart the Watchdog timer.
//!
//! \note this is use to feed the watch dog.
//!
//! \return None.
//
//*****************************************************************************
void 
WDTimerRestart(void)
{   
    SysCtlKeyAddrUnlock();
    xHWREG(WDT_WTCR) |= WDT_WTCR_WTR;
    SysCtlKeyAddrLock();
}

//*****************************************************************************
//
//! DMA channel 0 transfer complete and error Interrupt Handler.
//!
//! The interrupt handler for DMA interrupts from the memory channel. 
//!
//! \return None.
//
//*****************************************************************************
void
DMA0IntHandler(void)
{
    unsigned long ulEvent = 0;
    
    ulEvent = xHWREG(DMA0_BASE + DMA_DSR_BCR) & 0x71000000;
    
    //
    // Clear the transfer complete interrupt flag
    //
    xHWREG(DMA0_BASE + DMA_DSR_BCR) |= DMA_DSR_BCR_DONE;
    if(g_psDMAChannelAssignTable[0].pfnDMAChannelHandlerCallback != 0)
    {
        g_psDMAChannelAssignTable[0].pfnDMAChannelHandlerCallback(0,0,ulEvent,0);
    }
}

//*****************************************************************************
//
//! Sets the transfer parameters for a DMA channel control structure.
//!
//! \param ulChannelID is the DMA channel ID.
//! \param ulMode is the type of DMA transfer.
//! \param pvSrcAddr is the source address for the transfer.
//! \param pvDstAddr is the destination address for the transfer.
//! \param ulTransferSize is the number of data items to transfer.
//!
//! This function is used to set the parameters for a DMA transfer.  These are
//! typically parameters that are changed often.  The function
//! DMAChannelControlSet() MUST be called at least once for this channel prior
//! to calling this function.
//!
//! The \e ulChannelStructIndex parameter should be the logical OR of the
//! channel number with one of \b DMA_PRI_SELECT or \b DMA_ALT_SELECT to
//! choose whether the primary or alternate data structure is used.
//!
//! The \e ulMode parameter should be one of the following values:
//!
//! - \b DMA_MODE_BASIC to perform a basic transfer based on request.
//! - \b DMA_MODE_AUTO to perform a transfer that will always complete once
//!   started even if request is removed.
//! .
//!
//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
//! location of the data to be transferred.  These addresses should be aligned
//! according to the item size.  The compiler will take care of this if the
//! pointers are pointing to storage of the appropriate data type.
//!
//! The \e ulTransferSize parameter is the number of data items, not the number
//! of bytes.
//!
//! The channel must also be enabled using DMAChannelEnable() after calling
//! this function.  The transfer will not begin until the channel has been set
//! up and enabled.  Note that the channel is automatically disabled after the
//! transfer is completed, meaning that DMAChannelEnable() must be called
//! again after setting up the next transfer.
//!
//! \note Great care must be taken to not modify a channel control structure
//! that is in use or else the results will be unpredictable, including the
//! possibility of undesired data transfers to or from memory or peripherals.
//! For BASIC and AUTO modes, it is safe to make changes when the channel is
//! disabled.
//!
//! \return None.
//
//*****************************************************************************
void 
DMAChannelTransferSet(unsigned long ulChannelID, void *pvSrcAddr, 
                       void *pvDstAddr, unsigned long ulTransferSize)
{
    //
    // Check the arguments.
    //
    xASSERT(xDMAChannelIDValid(ulChannelID));
    xASSERT((ulTransferSize >= 0)&&(ulTransferSize <= DMA_DSR_BCR_BCR_M));
	
    xHWREG(g_psDMAChannelAddress[ulChannelID] + DMA_SAR) = (unsigned long)pvSrcAddr;
    xHWREG(g_psDMAChannelAddress[ulChannelID] + DMA_DAR) = (unsigned long)pvDstAddr;
	
    xHWREG(g_psDMAChannelAddress[ulChannelID] + DMA_DSR_BCR) &= ~DMA_DSR_BCR_BCR_M;
    xHWREG(g_psDMAChannelAddress[ulChannelID] + DMA_DSR_BCR) |= ulTransferSize;  
}

//*****************************************************************************
//
//! \brief Set ADC Voltage Reference.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulRefVol is the Voltage Reference that you will set.
//!
//! Set ADC Voltage Reference.
//!
//! \return None.
//
//*****************************************************************************
void
ADCRefVoltageSet(unsigned long ulBase, unsigned long ulRefVol)
{
    //
    // Check the arguments
    //
    xASSERT(ulBase == ADC_BASE);
    xASSERT((ulRefVol == ADC_COMP_REF_VOL_DEFAULT) ||
            (ulRefVol == ADC_COMP_REF_VOL_ALTERNATE));

    //
    // Set ADC Voltage Reference.
    //
    xHWREG(ulBase + ADC0_SC2) &= ~ADC_SC2_REFSEL_M;
    xHWREG(ulBase + ADC0_SC2) |= ulRefVol; 
}