本文整理汇总了C++中writereg函数的典型用法代码示例。如果您正苦于以下问题：C++ writereg函数的具体用法？C++ writereg怎么用？C++ writereg使用的例子？那么, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了writereg函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: ipac_write
static inline void
ipac_write(struct IsdnCardState *cs, u8 offset, u8 value)
{
writereg(cs, cs->hw.elsa.isac, offset, value);
}示例2: WriteISAC_IPAC
static void
WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset | 0x80, value);
}示例3: elsa_interrupt
static irqreturn_t
elsa_interrupt(int intno, void *dev_id)
{
struct IsdnCardState *cs = dev_id;
u_long flags;
u_char val;
int icnt = 5;
if ((cs->typ == ISDN_CTYPE_ELSA_PCMCIA) && (*cs->busy_flag == 1)) {
/* The card tends to generate interrupts while being removed
causing us to just crash the kernel. bad. */
printk(KERN_WARNING "Elsa: card not available!\n");
return IRQ_NONE;
}
spin_lock_irqsave(&cs->lock, flags);
#if ARCOFI_USE
if (cs->hw.elsa.MFlag) {
val = serial_inp(cs, UART_IIR);
if (!(val & UART_IIR_NO_INT)) {
debugl1(cs, "IIR %02x", val);
rs_interrupt_elsa(cs);
}
}
#endif
val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40);
Start_HSCX:
if (val) {
hscx_int_main(cs, val);
}
val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA);
Start_ISAC:
if (val) {
isac_interrupt(cs, val);
}
val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40);
if (val && icnt) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
icnt--;
goto Start_HSCX;
}
val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA);
if (val && icnt) {
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC IntStat after IntRoutine");
icnt--;
goto Start_ISAC;
}
if (!icnt)
printk(KERN_WARNING"ELSA IRQ LOOP\n");
writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF);
writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF);
if (cs->hw.elsa.status & ELIRQF_TIMER_AKTIV) {
if (!TimerRun(cs)) {
/* Timer Restart */
byteout(cs->hw.elsa.timer, 0);
cs->hw.elsa.counter++;
}
}
#if ARCOFI_USE
if (cs->hw.elsa.MFlag) {
val = serial_inp(cs, UART_MCR);
val ^= 0x8;
serial_outp(cs, UART_MCR, val);
val = serial_inp(cs, UART_MCR);
val ^= 0x8;
serial_outp(cs, UART_MCR, val);
}
#endif
if (cs->hw.elsa.trig)
byteout(cs->hw.elsa.trig, 0x00);
writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0);
writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0);
writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0x0);
spin_unlock_irqrestore(&cs->lock, flags);
return IRQ_HANDLED;
}示例4: WriteJADE
static void
WriteJADE(struct IsdnCardState *cs, int jade, u_char offset, u_char value)
{
writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)), value);
}示例5: setup_sct_quadro
//.........这里部分代码省略.........
pci_ioaddr1 += 0x80;
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, pci_ioaddr1);
dev_a8->resource[1].start = pci_ioaddr1;
}
#endif
}
if (!pci_irq) {
printk(KERN_WARNING "HiSax: Scitel Quadro (%s): No IRQ\n",
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
"No IO base address(es)\n",
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
cs->irq = pci_irq;
cs->irq_flags |= IRQF_SHARED;
cs->hw.ax.plx_adr = pci_ioaddr1;
switch (cs->subtyp) {
case 1:
cs->hw.ax.base = pci_ioaddr5 + 0x00;
if (sct_alloc_io(pci_ioaddr1, 128))
return (0);
if (sct_alloc_io(pci_ioaddr5, 64))
return (0);
writereg(pci_ioaddr5, pci_ioaddr5 + 4,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
IPAC_MASK, 0xFF);
break;
case 2:
cs->hw.ax.base = pci_ioaddr4 + 0x08;
if (sct_alloc_io(pci_ioaddr4, 64))
return (0);
break;
case 3:
cs->hw.ax.base = pci_ioaddr3 + 0x10;
if (sct_alloc_io(pci_ioaddr3, 64))
return (0);
break;
case 4:
cs->hw.ax.base = pci_ioaddr2 + 0x20;
if (sct_alloc_io(pci_ioaddr2, 64))
return (0);
break;
}
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
printk(KERN_INFO "HiSax: Scitel Quadro (%s) configured at "
"0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
sct_quadro_subtypes[cs->subtyp],
cs->hw.ax.plx_adr,
cs->hw.ax.base,
cs->hw.ax.data_adr,
cs->irq);
test_and_set_bit(HW_IPAC, &cs->HW_Flags);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
cs->readisacfifo = &ReadISACfifo;
cs->writeisacfifo = &WriteISACfifo;
cs->BC_Read_Reg = &ReadHSCX;
cs->BC_Write_Reg = &WriteHSCX;
cs->BC_Send_Data = &hscx_fill_fifo;
cs->cardmsg = &BKM_card_msg;
cs->irq_func = &bkm_interrupt_ipac;
printk(KERN_INFO "HiSax: Scitel Quadro (%s): IPAC Version %d\n",
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
return (1);
}示例6: WriteISAC
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
cs->hw.hfc.cip = offset;
writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value);
}示例7: isac_interrupt
static inline void
isac_interrupt(struct IsdnCardState *sp, u_char val)
{
u_char exval;
struct sk_buff *skb;
unsigned int count;
char tmp[32];
if (sp->debug & L1_DEB_ISAC) {
sprintf(tmp, "ISAC interrupt %x", val);
debugl1(sp, tmp);
}
if (val & 0x80) { /* RME */
exval = readreg(sp->isac, ISAC_RSTA);
if ((exval & 0x70) != 0x20) {
if (exval & 0x40)
if (sp->debug & L1_DEB_WARN)
debugl1(sp, "ISAC RDO");
if (!(exval & 0x20))
if (sp->debug & L1_DEB_WARN)
debugl1(sp, "ISAC CRC error");
writereg(sp->isac, ISAC_CMDR, 0x80);
} else {
count = readreg(sp->isac, ISAC_RBCL) & 0x1f;
if (count == 0)
count = 32;
isac_empty_fifo(sp, count);
if ((count = sp->rcvidx) > 0) {
if (!(skb = alloc_skb(count, GFP_ATOMIC)))
printk(KERN_WARNING "AVM: D receive out of memory\n");
else {
SET_SKB_FREE(skb);
memcpy(skb_put(skb, count), sp->rcvbuf, count);
skb_queue_tail(&sp->rq, skb);
}
}
}
sp->rcvidx = 0;
isac_sched_event(sp, ISAC_RCVBUFREADY);
}
if (val & 0x40) { /* RPF */
isac_empty_fifo(sp, 32);
}
if (val & 0x20) { /* RSC */
/* never */
if (sp->debug & L1_DEB_WARN)
debugl1(sp, "ISAC RSC interrupt");
}
if (val & 0x10) { /* XPR */
if (sp->tx_skb)
if (sp->tx_skb->len) {
isac_fill_fifo(sp);
goto afterXPR;
} else {
dev_kfree_skb(sp->tx_skb, FREE_WRITE);
sp->tx_cnt = 0;
sp->tx_skb = NULL;
}
if ((sp->tx_skb = skb_dequeue(&sp->sq))) {
sp->tx_cnt = 0;
isac_fill_fifo(sp);
} else
isac_sched_event(sp, ISAC_XMTBUFREADY);
}
afterXPR:
if (val & 0x04) { /* CISQ */
sp->ph_state = (readreg(sp->isac, ISAC_CIX0) >> 2)
& 0xf;
if (sp->debug & L1_DEB_ISAC) {
sprintf(tmp, "l1state %d", sp->ph_state);
debugl1(sp, tmp);
}
isac_new_ph(sp);
}示例8: setregbank
/*---------------------------------------------------------------------------*/
static void
setregbank(uint8_t bank)
{
writereg(ECON1, (readreg(ECON1) & 0xfc) | (bank & 0x03));
}示例9: eim_init
//.........这里部分代码省略.........
const int BCM = 1; /* Burst clock mode (set c ontinuous here) */
u32 GCR1, GCR2, RCR1, RCR2, WCR1, WEIMCR;
u32 temp_clk;
const int emi_slow_podf = 7;
iomux_v3_cfg_t iomux_cs2 = MX51_PAD_EIM_CS2__EIM_CS2;
iomux_v3_cfg_t iomux_dtack = MX51_PAD_EIM_DTACK__GPIO2_31;
iomux_v3_cfg_t iomux_event = MX51_PAD_GPIO1_5__SDMA_EXT_EVENT;
mxc_iomux_v3_setup_pad(iomux_cs2);
mxc_iomux_v3_setup_pad(iomux_dtack);
mxc_iomux_v3_setup_pad(iomux_event);
/*
* Change the clock divider for EMI bus from divide-by-7 to divide-by-8, so
* that the bus frequency is below 90 MHz, in accordance with footnote 4 in
* section 4.6.7.3 in the datasheet. This is necessary to prevent bus errors
* as the device heats up.
*/
temp_clk = __raw_readl( MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)+ MXC_CCM_CBCDR );
__raw_writel( (temp_clk & (~0x1c00000)) | bitfield(22, 3, emi_slow_podf),
MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)+ MXC_CCM_CBCDR );
if (gpio_request(event_gpio_num, "xillybus")) {
printk(KERN_ERR THIS "GPIO pin %i is already in use\n", event_gpio_num);
return -ENODEV;
}
gpio_direction_input(event_gpio_num);
GCR1 = 0x0111008f |
bitfield(28, 4, PSZ) |
bitfield(23, 1, AUS) |
bitfield(20, 3, CSREC) |
bitfield(14, 2, BCS) |
bitfield(12, 2, BCD) |
bitfield(11, 1, WC) |
bitfield(8, 3, BL) |
bitfield(5, 1, RFL) |
bitfield(4, 1, WFL);
GCR2 = bitfield(0, 2, ADH);
RCR1 =
bitfield(24, 6, RWSC) |
bitfield(20, 3, ADVA) |
bitfield(16, 3, ADVN) |
bitfield(12, 3, OEA) |
bitfield(4, 3, CSA);
RCR2 =
bitfield(8, 2, RL) |
bitfield(4, 3, BEA) |
bitfield(3, 1, BE);
WCR1 =
bitfield(30, 1, !BE) |
bitfield(24, 6, WWSC) |
bitfield(21, 3, ADVA) |
bitfield(18, 3, ADVN) |
bitfield(15, 3, BEA) |
bitfield(9, 3, WEA) |
bitfield(3, 3, CSA);
WEIMCR =
bitfield(5, 1, INTPOL) |
bitfield(4, 1, INTEN) |
bitfield(1, 2, GBCD) |
bitfield(0, 1, BCM);
writereg(0x30, GCR1);
writereg(0x34, GCR2);
writereg(0x38, RCR1);
writereg(0x3c, RCR2);
writereg(0x40, WCR1);
writereg(0x90, WEIMCR);
if (!request_mem_region(MX51_CS2_BASE_ADDR, SZ_64K, "xillybus_sdma")) {
printk(KERN_ERR THIS "request_mem_region failed. Aborting.\n");
return -ENODEV;
}
cs2_base = ioremap_nocache(MX51_CS2_BASE_ADDR, SZ_64K);
if (!cs2_base) {
printk(KERN_WARNING THIS "Failed to obtain I/O space\n");
ret = -ENODEV;
goto failed_ioremap;
}
return 0;
failed_ioremap:
release_mem_region(MX51_CS2_BASE_ADDR, SZ_64K);
return ret;
}示例10: Sedl_card_msg
static int
Sedl_card_msg(struct IsdnCardState *cs, int mt, void *arg)
{
u_long flags;
switch (mt) {
case CARD_RESET:
spin_lock_irqsave(&cs->lock, flags);
reset_sedlbauer(cs);
spin_unlock_irqrestore(&cs->lock, flags);
return(0);
case CARD_RELEASE:
if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) {
spin_lock_irqsave(&cs->lock, flags);
writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx,
ISAR_IRQBIT, 0);
writereg(cs->hw.sedl.adr, cs->hw.sedl.isac,
ISAC_MASK, 0xFF);
reset_sedlbauer(cs);
writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx,
ISAR_IRQBIT, 0);
writereg(cs->hw.sedl.adr, cs->hw.sedl.isac,
ISAC_MASK, 0xFF);
spin_unlock_irqrestore(&cs->lock, flags);
}
release_io_sedlbauer(cs);
return(0);
case CARD_INIT:
spin_lock_irqsave(&cs->lock, flags);
reset_sedlbauer(cs);
if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) {
clear_pending_isac_ints(cs);
writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx,
ISAR_IRQBIT, 0);
initisac(cs);
initisar(cs);
/* Reenable all IRQ */
cs->writeisac(cs, ISAC_MASK, 0);
/* RESET Receiver and Transmitter */
cs->writeisac(cs, ISAC_CMDR, 0x41);
} else {
inithscxisac(cs, 3);
}
spin_unlock_irqrestore(&cs->lock, flags);
return(0);
case CARD_TEST:
return(0);
case MDL_INFO_CONN:
if (cs->subtyp != SEDL_SPEEDFAX_PYRAMID)
return(0);
spin_lock_irqsave(&cs->lock, flags);
if ((long) arg)
cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED2;
else
cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED1;
byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
spin_unlock_irqrestore(&cs->lock, flags);
break;
case MDL_INFO_REL:
if (cs->subtyp != SEDL_SPEEDFAX_PYRAMID)
return(0);
spin_lock_irqsave(&cs->lock, flags);
if ((long) arg)
cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED2;
else
cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED1;
byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off);
spin_unlock_irqrestore(&cs->lock, flags);
break;
}
return(0);
}示例11: net_open
/* Open/initialize the board. This is called (in the current kernel)
sometime after booting when the 'ifconfig' program is run.
This routine should set everything up anew at each open, even
registers that "should" only need to be set once at boot, so that
there is non-reboot way to recover if something goes wrong.
*/
static int
net_open(struct net_device *dev)
{
struct net_local *lp = (struct net_local *)dev->priv;
int result = 0;
write_irq(dev, lp->chip_type, 0);
/* irq2dev_map[0] = dev; */
writereg(dev, PP_BusCTL, 0); /* ints off! */
#ifdef CONFIG_UCSIMM
*(volatile unsigned short *)0xfffff302 |= 0x0080; /* +ve pol irq */
dev->irq = IRQ5_IRQ_NUM;
if (request_irq(dev->irq | IRQ_MACHSPEC,
cs8900_interrupt,
IRQ_FLG_STD,
"CrystalLAN_cs8900a", NULL))
panic("Unable to attach cs8900 intr\n");
#endif
#ifdef CONFIG_ARCH_ATMEL
/* Set IRQ1 with high level sensitive & priority level 6. */
*(volatile unsigned int *) AIC_SMR(IRQ_IRQ1) = 0x46;
/* We use IRQ_IRQ1 for the network interrupt */
dev->irq = IRQ_IRQ1;
if (request_irq(dev->irq,
cs8900_interrupt,
IRQ_FLG_STD,
"CrystalLAN_cs8900a", NULL))
panic("Unable to attach cs8900 intr\n");
#endif
#if defined (CONFIG_BOARD_UCLINKII) || \
defined (CONFIG_BOARD_EVS3C4530LII) || \
defined (CONFIG_BOARD_EVS3C4530HEI)
*(volatile unsigned int *)IOPCON0 |= (xINTREQ0_ENABLE | xINTREQ0_ACT_HI);
dev->irq = _IRQ0;
if (request_irq (dev->irq, cs8900_interrupt, 0,
"Crystal_CS8900", dev))
panic("Unable to attach cs8900 intr\n");
#endif
#ifdef CONFIG_ALMA_ANS
/* We use positive polarity IRQ3 as a network interrupt */
ICR |= ICR_POL3;
dev->irq = IRQ3_IRQ_NUM;
if (request_irq(dev->irq | IRQ_MACHSPEC,
cs8900_interrupt,
IRQ_FLG_STD,
"CrystalLAN_cs8900a", NULL))
panic("Unable to attach cs8900 intr\n");
#endif
/* set the Ethernet address */
set_mac_address(dev, dev->dev_addr);
/* Set the LineCTL */
lp->linectl = 0;
/* check to make sure that they have the "right" hardware available */
switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) {
case A_CNF_MEDIA_10B_T:
result = lp->adapter_cnf & A_CNF_10B_T;
break;
case A_CNF_MEDIA_AUI:
result = lp->adapter_cnf & A_CNF_AUI;
break;
case A_CNF_MEDIA_10B_2:
result = lp->adapter_cnf & A_CNF_10B_2;
break;
default:
result = lp->adapter_cnf &
(A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2);
}
if (!result) {
printk("%s: EEPROM is configured for unavailable media\n", dev->name);
release_irq:
writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) & ~(SERIAL_TX_ON | SERIAL_RX_ON));
/* so subsequent opens don't fail we release the IRQ ...MaTed--- */
free_irq( dev->irq, dev);
/* irq2dev_map[dev->irq] = 0; */
return -EAGAIN;
}
/* set the hardware to the configured choice */
switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) {
case A_CNF_MEDIA_10B_T:
result = detect_tp(dev);
if (!result) {
printk("%s: 10Base-T (RJ-45) has no cable\n", dev->name);
//.........这里部分代码省略.........
示例12: enc28j60_send
/*---------------------------------------------------------------------------*/
int
enc28j60_send(const uint8_t *data, uint16_t datalen)
{
uint16_t dataend;
if(!initialized) {
return -1;
}
/*
1. Appropriately program the ETXST pointer to point to an unused
location in memory. It will point to the per packet control
byte. In the example, it would be programmed to 0120h. It is
recommended that an even address be used for ETXST.
2. Use the WBM SPI command to write the per packet control byte,
the destination address, the source MAC address, the
type/length and the data payload.
3. Appropriately program the ETXND pointer. It should point to the
last byte in the data payload. In the example, it would be
programmed to 0156h.
4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE to enable an
interrupt when done (if desired).
5. Start the transmission process by setting
ECON1.TXRTS.
*/
setregbank(ERXTX_BANK);
/* Set up the transmit buffer pointer */
writereg(ETXSTL, TX_BUF_START & 0xff);
writereg(ETXSTH, TX_BUF_START >> 8);
writereg(EWRPTL, TX_BUF_START & 0xff);
writereg(EWRPTH, TX_BUF_START >> 8);
/* Write the transmission control register as the first byte of the
output packet. We write 0x00 to indicate that the default
configuration (the values in MACON3) will be used. */
writedatabyte(0x00); /* MACON3 */
writedata(data, datalen);
/* Write a pointer to the last data byte. */
dataend = TX_BUF_START + datalen;
writereg(ETXNDL, dataend & 0xff);
writereg(ETXNDH, dataend >> 8);
/* Clear EIR.TXIF */
clearregbitfield(EIR, EIR_TXIF);
/* Don't care about interrupts for now */
/* Send the packet */
setregbitfield(ECON1, ECON1_TXRTS);
while((readreg(ECON1) & ECON1_TXRTS) > 0);
#if DEBUG
if((readreg(ESTAT) & ESTAT_TXABRT) != 0) {
uint16_t erdpt;
uint8_t tsv[7];
erdpt = (readreg(ERDPTH) << 8) | readreg(ERDPTL);
writereg(ERDPTL, (dataend + 1) & 0xff);
writereg(ERDPTH, (dataend + 1) >> 8);
readdata(tsv, sizeof(tsv));
writereg(ERDPTL, erdpt & 0xff);
writereg(ERDPTH, erdpt >> 8);
PRINTF("enc28j60: tx err: %d: %02x:%02x:%02x:%02x:%02x:%02x\n"
" tsv: %02x%02x%02x%02x%02x%02x%02x\n", datalen,
0xff & data[0], 0xff & data[1], 0xff & data[2],
0xff & data[3], 0xff & data[4], 0xff & data[5],
tsv[6], tsv[5], tsv[4], tsv[3], tsv[2], tsv[1], tsv[0]);
} else {示例13: setregbank
/*---------------------------------------------------------------------------*/
static void
setregbank(uint8_t new_bank)
{
writereg(ECON1, (readreg(ECON1) & 0xfc) | (new_bank & 0x03));
bank = new_bank;
}示例14: setup_sct_quadro
//.........这里部分代码省略.........
#endif /* End HACK */
}
if (!pci_irq) { /* IRQ range check ?? */
printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
/* Take over */
cs->irq = pci_irq;
cs->irq_flags |= SA_SHIRQ;
/* pci_ioaddr1 is unique to all subdevices */
/* pci_ioaddr2 is for the fourth subdevice only */
/* pci_ioaddr3 is for the third subdevice only */
/* pci_ioaddr4 is for the second subdevice only */
/* pci_ioaddr5 is for the first subdevice only */
cs->hw.ax.plx_adr = pci_ioaddr1;
/* Enter all ipac_base addresses */
switch(cs->subtyp) {
case 1:
cs->hw.ax.base = pci_ioaddr5 + 0x00;
if (sct_alloc_io(pci_ioaddr1, 128))
return(0);
if (sct_alloc_io(pci_ioaddr5, 64))
return(0);
/* disable all IPAC */
writereg(pci_ioaddr5, pci_ioaddr5 + 4,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
IPAC_MASK, 0xFF);
break;
case 2:
cs->hw.ax.base = pci_ioaddr4 + 0x08;
if (sct_alloc_io(pci_ioaddr4, 64))
return(0);
break;
case 3:
cs->hw.ax.base = pci_ioaddr3 + 0x10;
if (sct_alloc_io(pci_ioaddr3, 64))
return(0);
break;
case 4:
cs->hw.ax.base = pci_ioaddr2 + 0x20;
if (sct_alloc_io(pci_ioaddr2, 64))
return(0);
break;
}
/* For isac and hscx data path */
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
cs->hw.ax.plx_adr,
cs->hw.ax.base,
cs->hw.ax.data_adr,
cs->irq);
test_and_set_bit(HW_IPAC, &cs->HW_Flags);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
cs->readisacfifo = &ReadISACfifo;
cs->writeisacfifo = &WriteISACfifo;
cs->BC_Read_Reg = &ReadHSCX;
cs->BC_Write_Reg = &WriteHSCX;
cs->BC_Send_Data = &hscx_fill_fifo;
cs->cardmsg = &BKM_card_msg;
cs->irq_func = &bkm_interrupt_ipac;
printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
return (1);
#else
printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
#endif /* CONFIG_PCI */
}示例15: reset
/*---------------------------------------------------------------------------*/
static void
reset(void)
{
PRINTF("enc28j60: resetting chip\n");
enc28j60_arch_spi_init();
/*
6.0 INITIALIZATION
Before the ENC28J60 can be used to transmit and receive packets,
certain device settings must be initialized. Depending on the
application, some configuration options may need to be
changed. Normally, these tasks may be accomplished once after
Reset and do not need to be changed thereafter.
6.1 Receive Buffer
Before receiving any packets, the receive buffer must be
initialized by programming the ERXST and ERXND pointers. All
memory between and including the ERXST and ERXND addresses will be
dedicated to the receive hardware. It is recommended that the
ERXST pointer be programmed with an even address.
Applications expecting large amounts of data and frequent packet
delivery may wish to allocate most of the memory as the receive
buffer. Applications that may need to save older packets or have
several packets ready for transmission should allocate less
memory.
When programming the ERXST pointer, the ERXWRPT registers will
automatically be updated with the same values. The address in
ERXWRPT will be used as the starting location when the receive
hardware begins writing received data. For tracking purposes, the
ERXRDPT registers should additionally be programmed with the same
value. To program ERXRDPT, the host controller must write to
ERXRDPTL first, followed by ERXRDPTH. See Section 7.2.4 “Freeing
Receive Buffer Space for more information
6.2 Transmission Buffer
All memory which is not used by the receive buffer is considered
the transmission buffer. Data which is to be transmitted should be
written into any unused space. After a packet is transmitted,
however, the hardware will write a seven-byte status vector into
memory after the last byte in the packet. Therefore, the host
controller should leave at least seven bytes between each packet
and the beginning of the receive buffer. No explicit action is
required to initialize the transmission buffer.
6.3 Receive Filters
The appropriate receive filters should be enabled or disabled by
writing to the ERXFCON register. See Section 8.0 “Receive Filters
for information on how to configure it.
6.4 Waiting For OST
If the initialization procedure is being executed immediately
following a Power-on Reset, the ESTAT.CLKRDY bit should be polled
to make certain that enough time has elapsed before proceeding to
modify the MAC and PHY registers. For more information on the OST,
see Section 2.2 “Oscillator Start-up Timer.
*/
/* Wait for OST */
while((readreg(ESTAT) & ESTAT_CLKRDY) == 0);
softreset();
setregbank(ERXTX_BANK);
/* Set up receive buffer */
writereg(ERXSTL, RX_BUF_START & 0xff);
writereg(ERXSTH, RX_BUF_START >> 8);
writereg(ERXNDL, RX_BUF_END & 0xff);
writereg(ERXNDH, RX_BUF_END >> 8);
writereg(ERDPTL, RX_BUF_START & 0xff);
writereg(ERDPTH, RX_BUF_START >> 8);
writereg(ERXRDPTL, RX_BUF_START & 0xff);
writereg(ERXRDPTH, RX_BUF_START >> 8);
/* Receive filters */
setregbank(EPKTCNT_BANK);
/* writereg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN |
ERXFCON_MCEN | ERXFCON_BCEN);*/
/* XXX: can't seem to get the unicast filter to work right now,
using promiscous mode for now. */
writereg(ERXFCON, 0);
/*
6.5 MAC Initialization Settings
Several of the MAC registers require configuration during
initialization. This only needs to be done once; the order of
programming is unimportant.
1. Clear the MARST bit in MACON2 to pull the MAC out of Reset.
2. Set the MARXEN bit in MACON1 to enable the MAC to receive
//.........这里部分代码省略.........