C++ spi_write函数代码示例

/**
 * Write bytes to slave device
 * 
 * @param self
 * @param args Tuple with data to write
 * @return none
 */
static PyObject* py_write(PyObject *self, PyObject* args){

    PyObject *tx_list;
    PyObject *item = 0;
    uint8_t tx_len = 0;

    /* Parse arguments */
    if(!PyArg_ParseTuple(args, "O!", &PyList_Type, &tx_list)){
        return NULL;
    }

    /* Get length of list */
    tx_len = PyList_Size(tx_list);

    /* Allocate memory for output buffer */
    uint8_t *tx_buffer = (uint8_t *)malloc(tx_len * sizeof(uint8_t));
    memset(tx_buffer, 0, sizeof(uint8_t));

    /* Populate output buffer */
    int i;
    for(i = 0; i < tx_len; i++){
        item = PyList_GetItem(tx_list, i);
        tx_buffer[i] = (uint8_t)PyInt_AsLong(item);
    }

    /* Send data */
    if(spi_write(fd, tx_buffer, tx_len) < 0){
        return PyErr_SetFromErrno(PyExc_IOError);
    }

    /* Do cleanup */
    free(tx_buffer);

    //Py_DECREF(item);
    Py_DECREF(tx_list);
    
    Py_RETURN_NONE;
}

/*
 * ad7816 data access by SPI
 */
static int ad7816_spi_read(struct ad7816_chip_info *chip, u16 *data)
{
	struct spi_device *spi_dev = chip->spi_dev;
	int ret = 0;

	gpio_set_value(chip->rdwr_pin, 1);
	gpio_set_value(chip->rdwr_pin, 0);
	ret = spi_write(spi_dev, &chip->channel_id, sizeof(chip->channel_id));
	if (ret < 0) {
		dev_err(&spi_dev->dev, "SPI channel setting error\n");
		return ret;
	}
	gpio_set_value(chip->rdwr_pin, 1);


	if (chip->mode == AD7816_PD) { /* operating mode 2 */
		gpio_set_value(chip->convert_pin, 1);
		gpio_set_value(chip->convert_pin, 0);
	} else { /* operating mode 1 */
		gpio_set_value(chip->convert_pin, 0);
		gpio_set_value(chip->convert_pin, 1);
	}

	while (gpio_get_value(chip->busy_pin))
		cpu_relax();

	gpio_set_value(chip->rdwr_pin, 0);
	gpio_set_value(chip->rdwr_pin, 1);
	ret = spi_read(spi_dev, (u8 *)data, sizeof(*data));
	if (ret < 0) {
		dev_err(&spi_dev->dev, "SPI data read error\n");
		return ret;
	}

	*data = be16_to_cpu(*data);

	return ret;
}

static int trf7970a_transmit(struct trf7970a *trf, struct sk_buff *skb,
		unsigned int len)
{
	unsigned int timeout;
	int ret;

	print_hex_dump_debug("trf7970a tx data: ", DUMP_PREFIX_NONE,
			16, 1, skb->data, len, false);

	ret = spi_write(trf->spi, skb->data, len);
	if (ret) {
		dev_err(trf->dev, "%s - Can't send tx data: %d\n", __func__,
				ret);
		return ret;
	}

	skb_pull(skb, len);

	if (skb->len > 0) {
		trf->state = TRF7970A_ST_WAIT_FOR_TX_FIFO;
		timeout = TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT;
	} else {
		if (trf->issue_eof) {
			trf->state = TRF7970A_ST_WAIT_TO_ISSUE_EOF;
			timeout = TRF7970A_WAIT_TO_ISSUE_ISO15693_EOF;
		} else {
			trf->state = TRF7970A_ST_WAIT_FOR_RX_DATA;
			timeout = trf->timeout;
		}
	}

	dev_dbg(trf->dev, "Setting timeout for %d ms, state: %d\n", timeout,
			trf->state);

	schedule_delayed_work(&trf->timeout_work, msecs_to_jiffies(timeout));

	return 0;
}

void writeData(uint8_t d)
{
	if (!g_HWSPI)
	{
		bbData(d);
		return;
	}
	memory_barrier();
	gpio_set(PIN_DC);
	gpio_clear(24);
	memory_barrier();
	pack.command = 0x100 | d;	// LoSSI 9-bit Parameter mode
	spi_start(0);				// Start SPI transfer to CS0 destination
	// Bypass spi_write function here
	//while (!HW.SPI0.CS.B.TXD); // ensure no reads
	//HW.SPI0.FIFO = pack.command;
	spi_write(d);
	spi_flush();
	memory_barrier();
	gpio_set(24);
	memory_barrier();
	//printf("Data:%.2X \n",pack.command);
}

int mmcsd_write_block(long long address, long size, int *data) {
	int r1;
	long i;

	mmcsd_select();
	r1 = 0xFF;
	r1 = mmcsd_write_single_block(address);

	if (r1) {
		mmcsd_deselect();
		return r1;
	}

	spi_write(DUMMY_BYTE);
	spi_write(DATA_START_TOKEN);

	for (i = 0; i < MMCSD_MAX_BLOCK_SIZE; ++i) {
		if (size) {
			spi_write(data[i]);
			size--;
		} else
			spi_write(0);
	}

	r1 = 0;
	spi_write(DUMMY_BYTE);
	spi_write(DUMMY_BYTE);
	r1 = mmcsd_get_r1();

	if (r1 & 0x0A) {
		return r1;
	}

	while (!input(MMC_DI))
		spi_write(DUMMY_BYTE);

	mmcsd_deselect();

	return 0;
}

static int sd_start_command(struct sd_host *host, struct sd_command *cmd)
{
	int retval = 0;

	/* select the card by driving CS low */
	spi_cs_low(host);

	/* send the command through the MOSI line */
	spi_write(host, cmd, sizeof(*cmd));

	/*
	 * Wait for the card response.
	 * Card responses come in the MISO line and have the most significant
	 * bit cleared.
	 */
	retval = spi_wait_for_resp(host, 0x00, 0x80, MMC_SPI_N_CR);

	if (retval > 0 && !(retval & 0x01) && cmd->cmd != 0x40)
		DBG("command = %d, response = 0x%02x\n", cmd->cmd & ~0x40,
		    retval);

	return retval;
}

/*
 * Erase one sector of flash memory at offset ``offset'' which is any
 * address within the sector which should be erased.
 *
 * Returns 0 if successful, non-zero otherwise.
 */
static int erase_sector(struct m25p *flash, u32 offset)
{
	DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n",
			flash->spi->dev.bus_id, __FUNCTION__,
			flash->mtd.erasesize / 1024, offset);

	/* Wait until finished previous write command. */
	if (wait_till_ready(flash))
		return 1;

	/* Send write enable, then erase commands. */
	write_enable(flash);

	/* Set up command buffer. */
	flash->command[0] = flash->erase_opcode;
	flash->command[1] = offset >> 16;
	flash->command[2] = offset >> 8;
	flash->command[3] = offset;

	spi_write(flash->spi, flash->command, sizeof(flash->command));

	return 0;
}

static int ak4104_spi_write(struct snd_soc_codec *codec, unsigned int reg,
			    unsigned int value)
{
	u8 *cache = codec->reg_cache;
	struct spi_device *spi = codec->control_data;

	if (reg >= codec->driver->reg_cache_size)
		return -EINVAL;

	/* only write to the hardware if value has changed */
	if (cache[reg] != value) {
		u8 tmp[2] = { (reg & AK4104_REG_MASK) | AK4104_WRITE, value };

		if (spi_write(spi, tmp, sizeof(tmp))) {
			dev_err(&spi->dev, "SPI write failed\n");
			return -EIO;
		}

		cache[reg] = value;
	}

	return 0;
}

// get module version
void bfin_get_module_version(ModuleVersion* vers) {
#if 1
#else
  u16 x;
  
  app_pause();
  // command
  spi_selectChip(BFIN_SPI, BFIN_SPI_NPCS);
  spi_write(BFIN_SPI, MSG_GET_MODULE_VERSION_COM);
  spi_unselectChip(BFIN_SPI, BFIN_SPI_NPCS);

  // major
  spi_selectChip(BFIN_SPI, BFIN_SPI_NPCS);
  spi_read(BFIN_SPI, &x);
  spi_unselectChip(BFIN_SPI, BFIN_SPI_NPCS);
  vers->maj = x;
  // minor
  spi_selectChip(BFIN_SPI, BFIN_SPI_NPCS);
  spi_read(BFIN_SPI, &x);
  spi_unselectChip(BFIN_SPI, BFIN_SPI_NPCS);
  vers->min = x;
  // rev
  vers->rev = 0;
  // rev high
  spi_selectChip(BFIN_SPI, BFIN_SPI_NPCS);
  spi_read(BFIN_SPI, &x);
  spi_unselectChip(BFIN_SPI, BFIN_SPI_NPCS);
  vers->rev |= ((x << 8) & 0xff00);
    // rev low
  spi_selectChip(BFIN_SPI, BFIN_SPI_NPCS);
  spi_read(BFIN_SPI, &x);
  spi_unselectChip(BFIN_SPI, BFIN_SPI_NPCS);
  vers->rev |= (x & 0x00ff);

  app_resume();
#endif
}

static ssize_t p61_dev_write(struct file *filp, const char *buf, size_t count,
                             loff_t *offset)
{
    int ret = -1;
    struct p61_dev *p61_dev;
    unsigned char tx_buffer[MAX_BUFFER_SIZE];

    P61_DBG_MSG(KERN_ALERT "p61_dev_write -Enter count %zu\n", count);

    p61_dev = filp->private_data;

    mutex_lock(&p61_dev->write_mutex);
    if (count > MAX_BUFFER_SIZE)
        count = MAX_BUFFER_SIZE;

    memset(&tx_buffer[0], 0, sizeof(tx_buffer));
    if (copy_from_user(&tx_buffer[0], &buf[0], count))
    {
        P61_ERR_MSG("%s : failed to copy from user space\n", __func__);
        mutex_unlock(&p61_dev->write_mutex);
        return -EFAULT;
    }
    /* Write data */
    ret = spi_write(p61_dev->spi, &tx_buffer[0], count);
    if (ret < 0)
    {
        ret = -EIO;
    }
    else
    {
        ret = count;
    }

    mutex_unlock(&p61_dev->write_mutex);
    P61_DBG_MSG(KERN_ALERT "p61_dev_write ret %d- Exit \n", ret);
    return ret;
}

static sint8 spi_rw(uint8 *pu8Mosi, uint8 *pu8Miso, uint16 u16Sz)
{
	uint8 u8Dummy = 0;
	uint8 u8SkipMosi = 0, u8SkipMiso = 0;
	uint16_t txd_data = 0;
	uint16_t rxd_data = 0;
	uint8_t uc_pcs;

	if (!pu8Mosi) {
		pu8Mosi = &u8Dummy;
		u8SkipMosi = 1;
	}
	else if(!pu8Miso) {
		pu8Miso = &u8Dummy;
		u8SkipMiso = 1;
	}
	else {
		return M2M_ERR_BUS_FAIL;
	}

	while (u16Sz) {
		txd_data = *pu8Mosi;
		spi_write(CONF_WINC_SPI, txd_data, 0, 0);

		/* Read SPI master data register. */
		spi_read(CONF_WINC_SPI, &rxd_data, &uc_pcs);
		*pu8Miso = rxd_data;

		u16Sz--;
		if (!u8SkipMiso)
			pu8Miso++;
		if (!u8SkipMosi)
			pu8Mosi++;
	}

	return M2M_SUCCESS;
}

void OLED_WR_Byte(uint8_t dat,uint8_t cmd)
{
#if	(FB_OLED && FB_IIC_OLED)
	if(cmd)
			{
   IIC_Start();
   Write_IIC_Byte(0x78);			//D/C#=0; R/W#=0
   Write_IIC_Byte(0x40);			//write data
   Write_IIC_Byte(dat);
   IIC_Stop();
		}
	else {
		IIC_Start();
   Write_IIC_Byte(0x78);            //Slave address,SA0=0
   Write_IIC_Byte(0x00);			//write command
   Write_IIC_Byte(dat); 
   IIC_Stop();
		
	}
#endif
#if	(FB_OLED && FB_SPI_OLED)
		//uint8_t i;
	uint8_t buffer[1];
	buffer[0] = dat;	
	if(cmd)
	  OLED_DC_Set();
	else 
	  OLED_DC_Clr();		  
	OLED_CS_Clr();
	spi_write(QN_SPI1, buffer, 1, oled_write_done);
	delay(100);
			 		  
	OLED_CS_Set();
	OLED_DC_Set();  
#endif

}

/* Primitive bulk write support for soc-cache.  The data pointed to by
 * `data' needs to already be in the form the hardware expects
 * including any leading register specific data.  Any data written
 * through this function will not go through the cache as it only
 * handles writing to volatile or out of bounds registers.
 */
static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
				     const void *data, size_t len)
{
	int ret;

	/* To ensure that we don't get out of sync with the cache, check
	 * whether the base register is volatile or if we've directly asked
	 * to bypass the cache.  Out of bounds registers are considered
	 * volatile.
	 */
	if (!codec->cache_bypass
	    && !snd_soc_codec_volatile_register(codec, reg)
	    && reg < codec->driver->reg_cache_size)
		return -EINVAL;

	switch (codec->control_type) {
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	case SND_SOC_I2C:
		ret = i2c_master_send(to_i2c_client(codec->dev), data, len);
		break;
#endif
#if defined(CONFIG_SPI_MASTER)
	case SND_SOC_SPI:
		ret = spi_write(to_spi_device(codec->dev), data, len);
		break;
#endif
	default:
		BUG();
	}

	if (ret == len)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
			     const char *buffer, size_t count) {
	struct spi_device *spi = to_spi_device(dev);
	struct pcf2123_sysfs_reg *r;
	u8 txbuf[2];
	unsigned long reg;
	unsigned long val;

	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	if (strict_strtoul(r->name, 16, &reg)
		|| strict_strtoul(buffer, 10, &val))
		return -EINVAL;

	txbuf[0] = PCF2123_WRITE | reg;
	txbuf[1] = val;
	ret = spi_write(spi, txbuf, sizeof(txbuf));
	if (ret < 0)
		return -EIO;
	pcf2123_delay_trec();
	return count;
}

static rt_size_t sd_mmc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
	rt_uint32_t count = size;
	rt_uint32_t sector = sd_mmc_partition.offset + pos;

	while (count)
	{
		if (sd_mmc_spi_read_open_PDCA(sector))
		{
			pdca_load_channel(PDCA_CHANNEL_SPI_RX, buffer, MMC_SECTOR_SIZE);
			pdca_load_channel(PDCA_CHANNEL_SPI_TX, (void *) dummy, MMC_SECTOR_SIZE);

			spi_write(SD_MMC_SPI, 0xFF);

			pdca_channel_rx->cr = AVR32_PDCA_TEN_MASK;
			pdca_channel_tx->cr = AVR32_PDCA_TEN_MASK;

			while (!(pdca_channel_rx->isr & AVR32_PDCA_ISR_TRC_MASK));

			sd_mmc_spi_read_close_PDCA();

			pdca_channel_rx->cr = AVR32_PDCA_TDIS_MASK;
			pdca_channel_tx->cr = AVR32_PDCA_TDIS_MASK;

			count--;
			buffer += MMC_SECTOR_SIZE;
		}
		else
		{
			rt_kprintf("Unable to initiate SD/MMC read command.\n");
			return 0;
		}
	}

	return size;
}