C++ spi_enable函数代码示例

void spi_write_a16byte(unsigned short spi_dat)
{
    spi_enable();
    //hi_ssp_writedata(spi_data);
    ssp_writew(SSP_DR, spi_dat);
    printk("spi_data:0x%x\n", spi_dat);
    msleep(10);
    spi_disable();
}

void spi_chanel_select(int channal)
{
	spi_enable();
	while(spi_busy());
	spi_desable();
	if(channal > 0)
		YX_GPIO_SC_PERCTRL1(12, 1);
	else  YX_GPIO_SC_PERCTRL1(12, 0);
}

void spi_init(_Bool isMsb, spi_op_mode_t opMode, spi_mode_t mode,
        spi_prescaler_t scaler)
{
    spi_set_msb_lsb(isMsb);
    spi_set_operation_mode(opMode);
    spi_set_prescaler(scaler);
    spi_set_mode(mode);
    spi_enable();
}

/**
 * \brief Initialize SPI as master.
 */
static void spi_master_initialize(void)
{
	/* Configure an SPI peripheral. */
	uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
	spi_enable_clock(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
	spi_disable_loopback(SPI_MASTER_BASE);

	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2));	// This sets the value of PCS within the Mode Register.
	spi_set_variable_peripheral_select(SPI_MASTER_BASE);					// PCS needs to be set within each transfer (PCS within SPI_TDR).
	spi_disable_peripheral_select_decode(SPI_MASTER_BASE);					// Each CS is to be connected to a single device.
	spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);

	/* Set communication parameters for CS0	*/
	spi_chip_sel = 0;
	spi_clk_freq = 100000;	// SPI CLK for RTC = 100kHz.
	spi_clk_pol = 1;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
			SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); 
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);		// CS rises after SPI transfers have completed.
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Set communication parameters for CS1	*/
	spi_chip_sel = 1;
	spi_clk_freq = 2000000;	// SPI CLK for RTC = 4MHz.
	spi_clk_pol = 0;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
	SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); 
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Set communication parameters for CS2	*/
	spi_chip_sel = 2;
	spi_clk_freq = 44000000;	// SPI CLK for MEM2 = 44MHz.
	spi_clk_pol = 1;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
	SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Enable SPI Communication */
	spi_enable(SPI_MASTER_BASE);
}

void spi_frequency(spi_t *obj, int hz) {
    spi_disable(obj);
    
    uint32_t PCLK = SystemCoreClock;
    
    obj->spi->DIV = PCLK/hz - 1;
    obj->spi->DLY = 0;
    spi_enable(obj);
}

/** Set up the SPI buses.
 * Set up the SPI peripheral, SPI clocks, SPI pins, and SPI pins' clocks.
 */
void spi_setup(void)
{
  /* Enable SPI1 periperal clock */
  RCC_APB2ENR |= RCC_APB2ENR_SPI1EN;
  /* Enable SPI2 periperal clock */
  RCC_APB1ENR |= RCC_APB1ENR_SPI2EN;
  /* Enable GPIO clocks for CS lines */
  RCC_AHB1ENR |= RCC_AHB1ENR_IOPAEN | RCC_AHB1ENR_IOPBEN;

  /* Setup CS line GPIOs */

  /* Deselect FPGA CS */
  gpio_set(GPIOA, GPIO4);
  /* Deselect configuration flash and front-end CS */
  gpio_set(GPIOB, GPIO11 | GPIO12);

  /* FPGA CS */
  gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO4);
  /* Configuration flash CS */
  gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO12);
  /* Front-end CS */
  gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO11);

  /* Setup SPI alternate function */
  gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
  gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
  gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 |
                  GPIO15);
  gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15);

  /* Setup SPI parameters. */
  spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0,
                  SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
  spi_enable_ss_output(SPI1); /* Required, see 25.3.1 section about NSS */
  spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0,
                  SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
  spi_enable_ss_output(SPI2); /* Required, see 25.3.1 section about NSS */

  /* Finally enable the SPI. */
  spi_enable(SPI1);
  spi_enable(SPI2);

  chMtxInit(&spi_mutex);
}

void spi_format(spi_t *obj, int bits, int mode, int slave) {
    int      DSS;      // DSS (data select size)
    int      polarity  = (mode & 0x2) ? 1 : 0;
    int      phase     = (mode & 0x1) ? 1 : 0;
    uint16_t tmp       = 0;
    uint16_t mask      = 0xf03;
    uint16_t wk_spcmd0;
    uint8_t  splw;

    switch (mode) {
        case 0:
        case 1:
        case 2:
        case 3:
            // Do Nothing
            break;
        default:
            error("SPI format error");
            return;
    }

    switch (bits) {
        case 8:
            DSS  = 0x7;
            splw = 0x20;
            break;
        case 16:
            DSS  = 0xf;
            splw = 0x40;
            break;
        case 32:
            DSS  = 0x2;
            splw = 0x60;
            break;
        default:
            error("SPI module don't support other than 8/16/32bits");
            return;
    }
    tmp |= phase;
    tmp |= (polarity << 1);
    tmp |= (DSS << 8);
    obj->bits = bits;

    spi_disable(obj);
    wk_spcmd0 = obj->spi->SPCMD0;
    wk_spcmd0 &= ~mask;
    wk_spcmd0 |= (mask & tmp);
    obj->spi->SPCMD0 = wk_spcmd0;
    obj->spi->SPDCR   = splw;
    if (slave) {
        obj->spi->SPCR &=~(1 << 3);  // MSTR to 0
    } else {
        obj->spi->SPCR |= (1 << 3);  // MSTR to 1
    }
    spi_enable(obj);
}

// Initialize Pin and SPI like specified into config file
void nrf24l01_init()
{
	// Init SPI pins
	ioport_set_pin_dir(CONF_NRF24L01_SS_PIN, IOPORT_DIR_INPUT);
	ioport_set_pin_mode(CONF_NRF24L01_SS_PIN, IOPORT_MODE_PULLUP);
	ioport_set_pin_dir(CONF_NRF24L01_MOSI_PIN, IOPORT_DIR_OUTPUT);
	ioport_set_pin_mode(CONF_NRF24L01_MOSI_PIN, IOPORT_MODE_PULLUP);
	ioport_set_pin_high(CONF_NRF24L01_MOSI_PIN);
	ioport_set_pin_dir(CONF_NRF24L01_MISO_PIN, IOPORT_DIR_INPUT);
	ioport_set_pin_dir(CONF_NRF24L01_SCK_PIN, IOPORT_DIR_OUTPUT);
	ioport_set_pin_high(CONF_NRF24L01_SCK_PIN);
	
	// Init nrf24l01 pins
	ioport_set_pin_dir(CONF_NRF24L01_CE_PIN, IOPORT_DIR_OUTPUT);
	ioport_set_pin_dir(CONF_NRF24L01_CSn_PIN, IOPORT_DIR_OUTPUT);
	ioport_set_pin_dir(CONF_NRF24L01_IRQ_PIN, IOPORT_DIR_INPUT);

	ioport_set_pin_low(CONF_NRF24L01_CE_PIN);
	spi_deselect_device(&CONF_NRF24L01_SPI, &nrf24l01_spi_device_conf);
	
	spi_master_init(&CONF_NRF24L01_SPI);
	spi_master_setup_device(&CONF_NRF24L01_SPI, &nrf24l01_spi_device_conf, SPI_MODE_0, CONF_NRF24L01_CLOCK_SPEED, 0);
	spi_enable(&CONF_NRF24L01_SPI);
	
	// Wait nrf24l01 power on reset
	delay_ms(Tpor);
	
	nrf24l01_power_off();
	
	// Reset registers to default state
	nrf24l01_write_register(NRF24L01_CONFIG_REG, NRF24L01_CONFIG_REG_DEF);
	nrf24l01_write_register(NRF24L01_STATUS_REG, NRF24L01_STATUS_REG_DEF);
	// TODO: reset all registers
	
	// Config parameters sets in CONF_NRF24L01
	nrf24l01_set_power_amplifier(CONF_NRF24L01_PA);
	nrf24l01_set_data_rate(CONF_NRF24L01_DATA_RATE);
	nrf24l01_set_crc(CONF_NRF24L01_CRC);
	nrf24l01_set_addr_len(CONF_NRF24L01_ADDR_LEN);

	uint8_t nrf24l01_rx_addr[5] = { CONF_NRF24L01_RX_ADDR };
	uint8_t nrf24l01_tx_addr[5] = { CONF_NRF24L01_TX_ADDR };

	nrf24l01_set_rx_addr(nrf24l01_rx_addr);
	nrf24l01_set_tx_addr(nrf24l01_tx_addr);
	
	nrf24l01_write_register(NRF24L01_RF_CH_REG, CONF_NRF24L01_RF_CHANNEL);
	nrf24l01_write_register(NRF24L01_RX_PW_P0_REG, CONF_NRF24L01_PAYLOAD);
	nrf24l01_write_register(NRF24L01_RX_PW_P1_REG, CONF_NRF24L01_PAYLOAD);
	
	// Power-up (Power Down -> Standby-I)
	uint8_t configReg = nrf24l01_read_register(NRF24L01_CONFIG_REG);
	nrf24l01_write_register(NRF24L01_CONFIG_REG, configReg | NRF24L01_PWR_UP_BM);
	
	delay_us(Tpd2stby);
}

void spi_frequency(spi_t *obj, int hz)
{
    spi_disable(obj);

    // rise DIV value if it cannot be divided
    obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
    obj->spi->DLY = 0;

    spi_enable(obj);
}

u8 A7105_ReadReg(u8 address)
{
    u8 data;

    CS_LO();
    spi_xfer(SPI2, 0x40 | address);
    spi_disable(SPI2);
    spi_set_bidirectional_receive_only_mode(SPI2);
    spi_enable(SPI2);
    int i;
    for(i = 0; i < 10; i++)
       ;
    spi_disable(SPI2);
    data = spi_read(SPI2);
    CS_HI();
    spi_set_unidirectional_mode(SPI2);
    spi_enable(SPI2);
    return data;
}

void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs)
{
    CMU_ClockEnable(cmuClock_HFPER, true);
    spi_preinit(obj, mosi, miso, clk, cs);
    CMU_ClockEnable(spi_get_clock_tree(obj), true);
    usart_init(obj, 100000, usartDatabits8, true, usartClockMode0);

    spi_enable_pins(obj, true, mosi, miso, clk, cs);
    spi_enable(obj, true);
}

unsigned char NRF24L01_Read_Buf(unsigned char reg,unsigned char *pBuf,unsigned char len)
{
		unsigned char status,u8_ctr;
		spi_enable();
  	status=spi_send(reg);   
		for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=spi_read(0XFF);//????
  	return status;   
	spi_disable();
	
}

/**
 * Initiates transmission of all bytes within the specified FIFO via SPI
 */
void spi_transmit_fifo(fifo_t* buffer)
{
//    if (spi_still_transmitting_fifo(my_spi))
//        return;

    spi_buffer = buffer;
    interrupt_enable(INTERRUPT_SPI);
    spi_interrupt_upon_READY_enable(my_spi);
    spi_enable(my_spi);
}

void test_spi_write() {
	// Copy of test_spi_write_ready()
	spi_enable(SPI0);
	spi_select_slave(SPI0, SPI_SELECTOR_0);
	TEST_ASSERT_TRUE(spi_tx_ready(SPI0));
	spi_write(SPI0, 0b01011010);
	TEST_ASSERT_FALSE(spi_tx_ready(SPI0));
	delay_ms(1);
	TEST_ASSERT_TRUE(spi_tx_ready(SPI0));
}

static void spi_drivers_setup()
{
	//SPI1 to extern
	gpio_set_spi_clk(GPIO_A,  GPIO_PIN_5);
	gpio_set_spi_miso(GPIO_A, GPIO_PIN_6);
	gpio_set_spi_mosi(GPIO_A, GPIO_PIN_7);
	spi_enable(SPI_1, 4000000, SPI_CLOCK_MODE_IDLE_LOW_RISING);
	boot_success("External SPI enabled at 4000000\n");

}