本文整理汇总了C++中soc_is_exynos4212函数的典型用法代码示例。如果您正苦于以下问题:C++ soc_is_exynos4212函数的具体用法?C++ soc_is_exynos4212怎么用?C++ soc_is_exynos4212使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了soc_is_exynos4212函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: s3c_i2c4_cfg_gpio
void s3c_i2c4_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos4210())
s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else
pr_err("failed to configure gpio for i2c4\n");
}
示例2: exynos_usb_hsic_exit
static int __maybe_unused exynos_usb_hsic_exit(struct platform_device *pdev)
{
u32 hsic_ctrl;
if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_usb_phy_control(USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
} else {
hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
}
return 0;
}
示例3: exynos_dma_init
static int __init exynos_dma_init(void)
{
if (soc_is_exynos4210()) {
exynos_device_pdma0.dev.platform_data = &exynos4210_pdma0_pdata;
exynos_device_pdma1.dev.platform_data = &exynos4210_pdma1_pdata;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_device_pdma0.dev.platform_data = &exynos4212_pdma0_pdata;
exynos_device_pdma1.dev.platform_data = &exynos4212_pdma1_pdata;
} else if (soc_is_exynos5210() || soc_is_exynos5250()) {
exynos_device_pdma0.dev.platform_data = &exynos5210_pdma0_pdata;
exynos_device_pdma1.dev.platform_data = &exynos5210_pdma1_pdata;
}
platform_add_devices(exynos_dmacs, ARRAY_SIZE(exynos_dmacs));
return 0;
}
示例4: s5p_usb_phy_suspend
int s5p_usb_phy_suspend(struct platform_device *pdev, int type)
{
int ret = 0;
#ifdef CONFIG_USB_OHCI_S5P
struct s5p_ohci_hcd *s5p_ohci = platform_get_drvdata(&s5p_device_ohci);
struct usb_hcd *ohci_hcd = s5p_ohci->hcd;
u32 phyclk;
#endif
if (exynos_usb_phy_clock_enable(pdev))
return 0;
mutex_lock(&phy_lock);
if (!strcmp(pdev->name, "s5p-ehci"))
clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
else if (!strcmp(pdev->name, "s5p-ohci"))
clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
if (usb_phy_control.flags)
goto done;
if (type == S5P_USB_PHY_HOST) {
if (soc_is_exynos4210() ||
soc_is_exynos4212() ||
soc_is_exynos4412()) {
#ifdef CONFIG_USB_OHCI_S5P
/* Set OHCI clock off when ohci_hcd is suspended */
if (ohci_hcd->state == HC_STATE_SUSPENDED) {
phyclk = readl(EXYNOS4_PHYCLK);
phyclk &= ~(PHY1_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
}
dev_info(&pdev->dev, "host_phy_susp:%d\n",
ohci_hcd->state);
#endif
ret = exynos4_usb_phy1_suspend(pdev);
} else
ret = exynos5_usb_phy_host_suspend(pdev);
}
done:
mutex_unlock(&phy_lock);
exynos_usb_phy_clock_disable(pdev);
return ret;
}
示例5: exynos_usb_phy_clock_disable
static int exynos_usb_phy_clock_disable(struct platform_device *pdev)
{
if (!phy_clk) {
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
phy_clk = clk_get(&pdev->dev, "usbotg");
else
phy_clk = clk_get(&pdev->dev, "usbhost");
if (IS_ERR(phy_clk)) {
dev_err(&pdev->dev, "Failed to get phy clock\n");
return PTR_ERR(phy_clk);
}
}
clk_disable(phy_clk);
return 0;
}
示例6: exynos_cpufreq_probe
static int exynos_cpufreq_probe(struct platform_device *pdev)
{
int ret = -EINVAL;
exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
if (!exynos_info)
return -ENOMEM;
exynos_info->dev = &pdev->dev;
if (soc_is_exynos4210())
ret = exynos4210_cpufreq_init(exynos_info);
else if (soc_is_exynos4212() || soc_is_exynos4412())
ret = exynos4x12_cpufreq_init(exynos_info);
else if (soc_is_exynos5250())
ret = exynos5250_cpufreq_init(exynos_info);
else
return 0;
if (ret)
goto err_vdd_arm;
if (exynos_info->set_freq == NULL) {
dev_err(&pdev->dev, "No set_freq function (ERR)\n");
goto err_vdd_arm;
}
arm_regulator = regulator_get(NULL, "vdd_arm");
if (IS_ERR(arm_regulator)) {
dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
goto err_vdd_arm;
}
/* Done here as we want to capture boot frequency */
locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;
if (!cpufreq_register_driver(&exynos_driver))
return 0;
dev_err(&pdev->dev, "failed to register cpufreq driver\n");
regulator_put(arm_regulator);
err_vdd_arm:
kfree(exynos_info);
return -EINVAL;
}
示例7: smp_init_cpus
void __init smp_init_cpus(void)
{
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos5250() || soc_is_exynos3250())
ncores = 2;
else if (soc_is_exynos4412() || soc_is_exynos5410()
|| soc_is_exynos4415() || soc_is_exynos3470())
ncores = 4;
else if (soc_is_exynos5260())
#ifdef CONFIG_EXYNOS5_MP
ncores = NR_CPUS;
#else
ncores = read_cpuid_mpidr() & 0x100 ? 4 : 2;
#endif
else if (soc_is_exynos5420())
示例8: exynos_cfg_i2s_gpio
static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
struct exynos_gpio_cfg exynos4_cfg[3] = {
{ EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5_cfg[3] = {
{ EXYNOS5_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5410_cfg[3] = {
{ EXYNOS5410_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5410_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5410_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5420_cfg[3] = {
{ EXYNOS5420_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5420_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5420_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
if (pdev->id < 0 || pdev->id > 2) {
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
else if (soc_is_exynos5410())
s3c_gpio_cfgpin_range(exynos5410_cfg[pdev->id].addr,
exynos5410_cfg[pdev->id].num, exynos5410_cfg[pdev->id].bit);
else if (soc_is_exynos5420())
s3c_gpio_cfgpin_range(exynos5420_cfg[pdev->id].addr,
exynos5420_cfg[pdev->id].num, exynos5420_cfg[pdev->id].bit);
else if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
return 0;
}
示例9: s5p_i2c_hdmiphy_set_platdata
void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd) {
pd = &default_i2c_data;
if (soc_is_exynos4210() ||
soc_is_exynos4212() || soc_is_exynos4412())
pd->bus_num = 8;
else if (soc_is_s5pv210())
pd->bus_num = 3;
else
pd->bus_num = 0;
}
npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
&s5p_device_i2c_hdmiphy);
}
示例10: s5p_usb_phy_exit
int s5p_usb_phy_exit(struct platform_device *pdev, int type)
{
int ret = -EINVAL;
if (exynos_usb_phy_clock_enable(pdev))
return ret;
mutex_lock(&phy_lock);
if (type == S5P_USB_PHY_HOST) {
if (soc_is_exynos4210())
ret = exynos4_usb_phy1_exit(pdev);
else if (soc_is_exynos4212() || soc_is_exynos4412())
ret = exynos4_usb_phy20_exit(pdev);
else
ret = exynos5_usb_phy20_exit(pdev);
if (!strcmp(pdev->name, "s5p-ehci"))
clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
else if (!strcmp(pdev->name, "s5p-ohci"))
clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
} else if (type == S5P_USB_PHY_DEVICE) {
/* set default usb phy tune */
if (pdev->dev.platform_data && soc_is_exynos4210())
ret = s5p_usb_phy0_tune(pdev->dev.platform_data, 1);
if (soc_is_exynos4210())
ret = exynos4_usb_phy0_exit(pdev);
else
ret = exynos_usb_dev_phy20_exit(pdev);
} else if (type == S5P_USB_PHY_DRD)
ret = exynos5_usb_phy30_exit(pdev);
else if (type == S5P_USB_PHY_OTGHOST) {
if (soc_is_exynos4210())
ret = exynos4_usb_phy0_exit(pdev);
else
ret = exynos_usb_dev_phy20_exit(pdev);
}
mutex_unlock(&phy_lock);
exynos_usb_phy_clock_disable(pdev);
return ret;
}
示例11: exynos4_sys_powerdown_conf
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = entry_cnt;
unsigned int tmp;
for (; count > 0; count--){
if(S5P_XUSBXTI_SYS != exynos4_pmu_config[count - 1].reg){
__raw_writel(exynos4_pmu_config[count - 1].val[mode],
exynos4_pmu_config[count - 1].reg);
}
else if(S5P_XUSBXTI_SYS == exynos4_pmu_config[count - 1].reg){
//printk("++++++++++++Terry++++++++++call_flag=%d , mode=%d \n", tc4_get_call_flg(),mode);
if((tc4_get_call_flg() != 1)||(mode != SYS_SLEEP)){
//printk("%s ------Terry1--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
__raw_writel(exynos4_pmu_config[count - 1].val[mode],
exynos4_pmu_config[count - 1].reg);
}
else
{
//printk("%s ------Terry2--------close xclk------tc4_get_call_flg=%d---\n",__func__,tc4_get_call_flg());
__raw_writel(0x1, exynos4_pmu_config[count - 1].reg);
}
}
}
if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
exynos4x12_c2c_pmu_conf[count].reg);
if (soc_is_exynos4212())
__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
exynos4212_c2c_pmu_conf[0].reg);
for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
printk("exynos4_config_for_c2c \n");
tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
tmp |= exynos4_config_for_c2c[count].val;
__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
}
}
}
示例12: exynos_dwmci_init
static int exynos_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
{
struct dw_mci *host = (struct dw_mci *)data;
/* Set Phase Shift Register */
if (soc_is_exynos4210()) {
host->pdata->sdr_timing = 0x00010001;
host->pdata->ddr_timing = 0x00020002;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
host->pdata->sdr_timing = 0x00010001;
host->pdata->ddr_timing = 0x00010002;
}
#ifdef CONFIG_SLP
host->pdata->sdr_timing = 0x00020001;
host->pdata->ddr_timing = 0x00020002;
#endif
return 0;
}
示例13: exynos4_init
int __init exynos4_init(void)
{
unsigned int value;
unsigned int tmp;
unsigned int i;
printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
/* set idle function */
pm_idle = exynos4_idle;
/*
* on exynos4x12, CMU reset system power register should to be set 0x0
*/
if (!soc_is_exynos4210()) {
for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++)
__raw_writel(0x0, exynos4_pmu_init_zero[i]);
}
/* set sw_reset function */
s5p_reset_hook = exynos4_sw_reset;
/* Disable auto wakeup from power off mode */
for (i = 0; i < num_possible_cpus(); i++) {
tmp = __raw_readl(S5P_ARM_CORE_OPTION(i));
tmp &= ~S5P_CORE_OPTION_DIS;
__raw_writel(tmp, S5P_ARM_CORE_OPTION(i));
}
if (soc_is_exynos4212() || soc_is_exynos4412()) {
value = __raw_readl(S5P_AUTOMATIC_WDT_RESET_DISABLE);
value &= ~S5P_SYS_WDTRESET;
__raw_writel(value, S5P_AUTOMATIC_WDT_RESET_DISABLE);
value = __raw_readl(S5P_MASK_WDT_RESET_REQUEST);
value &= ~S5P_SYS_WDTRESET;
//__raw_writel(value, S5P_MASK_WDT_RESET_REQUEST);
//Temperory ignore ISP reset, for ISP test. Jiangshanbin120405
__raw_writel((value | (1<< 26)), S5P_MASK_WDT_RESET_REQUEST);
}
return sysdev_register(&exynos4_sysdev);
}
示例14: mali_dvfs_table_update
static mali_bool mali_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(soc_is_exynos4412()) {
/*check it's pega-prime or pega-Q*/
if(samsung_rev() < EXYNOS4412_REV_2_0) {
step_num = MALI_DVFS_STEPS-1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_4412_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
/* For Pega-Prime e-fuse, add 25mV from default ASV table*/
/* else if((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}*/
/* pega-prime default ASV table */
else {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
}
else if(soc_is_exynos4212()) {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_4212_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
return MALI_TRUE;
}
示例15: exynos_usb_mux_change
static void exynos_usb_mux_change(struct platform_device *pdev, int val)
{
u32 is_host;
if(val)
return;
if (soc_is_exynos4212() || soc_is_exynos4412()) {
is_host = readl(EXYNOS4_USB_CFG);
writel(val, EXYNOS4_USB_CFG);
} else {
is_host = readl(EXYNOS5_USB_CFG);
writel(val, EXYNOS5_USB_CFG);
}
if (is_host != val)
dev_dbg(&pdev->dev, "Change USB MUX from %s to %s",
is_host ? "Host" : "Device",
val ? "Host" : "Device");
}