本文整理汇总了C++中sim_activate函数的典型用法代码示例。如果您正苦于以下问题：C++ sim_activate函数的具体用法？C++ sim_activate怎么用？C++ sim_activate使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了sim_activate函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: i8274_svc
t_stat i8274_svc (UNIT *uptr)
{
int32 temp;
sim_activate (&i8274_unit, i8274_unit.wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG)
return temp; /* no char or error? */
i8274_unit.buf = temp & 0xFF; /* Save char */
rr0a |= 0x01; /* Set rx char ready */
/* Do any special character handling here */
i8274_unit.pos++;
return SCPE_OK;
}示例2: ptr_svc
t_stat ptr_svc (UNIT *uptr)
{
int32 temp;
if ((uptr->flags & UNIT_ATT) == 0) { /* attached? */
if (ptr_wait) /* if wait, clr ioh */
ptr_wait = ioh = 0;
if ((cpls & CPLS_PTR) || ptr_stopioe)
return SCPE_UNATT;
return SCPE_OK;
}
if ((uptr->flags & UNIT_ASCII) && (ptr_state == 0)) /* ASCII mode, alpha read? */
temp = ptr_get_ascii (uptr); /* get processed char */
else if ((temp = getc (uptr->fileref)) != EOF) /* no, get raw char */
uptr->pos = uptr->pos + 1; /* if not eof, count */
if (temp == EOF) { /* end of file? */
if (ptr_wait) /* if wait, clr ioh */
ptr_wait = ioh = 0;
if (feof (uptr->fileref)) {
if ((cpls & CPLS_PTR) || ptr_stopioe)
printf ("PTR end of file\n");
else return SCPE_OK;
}
else perror ("PTR I/O error");
clearerr (uptr->fileref);
return SCPE_IOERR;
}
if (ptr_state == 0) /* alpha */
uptr->buf = temp & 0377;
else if (temp & 0200) { /* binary */
ptr_state = ptr_state - 6;
uptr->buf = uptr->buf | ((temp & 077) << ptr_state);
}
if (ptr_state == 0) { /* done? */
if (cpls & CPLS_PTR) { /* completion pulse? */
iosta = iosta & ~IOS_PTR; /* clear flag */
IO = uptr->buf; /* fill IO */
ios = 1; /* restart */
cpls = cpls & ~CPLS_PTR;
}
else { /* no, interrupt */
iosta = iosta | IOS_PTR; /* set flag */
dev_req_int (ptr_sbs); /* req interrupt */
}
}
else sim_activate (uptr, uptr->wait); /* get next char */
return SCPE_OK;
}示例3: tto_svc
t_stat tto_svc (UNIT *uptr)
{
int32 c;
t_stat r;
c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags) | TTUF_KSR);
if (c >= 0) {
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* try again */
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
}
}
dev_done = dev_done | INT_TTO; /* set ready */
uptr->pos = uptr->pos + 1;
return SCPE_OK;
}示例4: ttp_reset
t_stat ttp_reset (DEVICE *dptr)
{
if (dptr->flags & DEV_DIS)
sim_cancel (&ttp_unit[TTI]);
else sim_activate (&ttp_unit[TTI], KBD_WAIT (ttp_unit[TTI].wait, lfc_poll));
sim_cancel (&ttp_unit[TTO]);
CLR_INT (v_TTP); /* clear int */
CLR_ENB (v_TTP);
CLR_INT (v_TTP + 1); /* disable int */
CLR_ENB (v_TTP + 1);
ttp_karm = ttp_tarm = 0; /* disarm int */
ttp_cmd = 0;
ttp_sta = 0;
ttp_kchp = 0;
return SCPE_OK;
}示例5: clk_reset
t_stat
clk_reset(DEVICE * dptr)
{
if (CPUT(HAS_LTCR)) /* reg there? */
clk_fie = clk_fnxm = 0;
else
clk_fie = clk_fnxm = 1; /* no, BEVENT */
clk_tps = clk_default; /* set default tps */
clk_csr = CSR_DONE; /* set done */
CLR_INT(CLK);
sim_rtcn_init(clk_unit.wait, TMR_CLK); /* init line clock */
sim_activate(&clk_unit, clk_unit.wait); /* activate unit */
tmr_poll = clk_unit.wait; /* set timer poll */
tmxr_poll = clk_unit.wait; /* set mux poll */
return SCPE_OK;
}示例6: fe_reset
t_stat fe_reset (DEVICE *dptr)
{
tmxr_set_console_units (&fe_unit[0], &fe_unit[1]);
fei_unit.buf = feo_unit.buf = 0;
M[FE_CTYIN] = M[FE_CTYOUT] = 0;
M[FE_KLININ] = M[FE_KLINOUT] = 0;
M[FE_KEEPA] = INT64_C(0003740000000); /* PARITY STOP, CRM, DP PAREN, CACHE EN, 1MSTMR, TRAPEN */
kaf_unit.u3 = 0;
kaf_unit.u4 = 0;
apr_flg = apr_flg & ~(APRF_ITC | APRF_CON);
sim_activate (&fei_unit, KBD_WAIT (fei_unit.wait, tmxr_poll));
sim_activate_after (&kaf_unit, kaf_unit.wait);
return SCPE_OK;
}示例7: rx_reset
t_stat rx_reset (DEVICE *dptr)
{
rx_csr = rx_dbr = 0; /* clear regs */
rx_esr = rx_ecode = 0; /* clear error */
rx_track = rx_sector = 0; /* clear addr */
rx_state = IDLE; /* ctrl idle */
CLR_INT (RX); /* clear int req */
sim_cancel (&rx_unit[1]); /* cancel drive 1 */
if (dptr->flags & DEV_DIS) sim_cancel (&rx_unit[0]); /* disabled? */
else if (rx_unit[0].flags & UNIT_BUF) { /* attached? */
rx_state = INIT_COMPLETE; /* yes, sched init */
sim_activate (&rx_unit[0], rx_swait * abs (1 - rx_unit[0].TRACK));
}
else rx_done (0, 0010); /* no, error */
return auto_config (0, 0); /* run autoconfig */
}示例8: tti_svc
t_stat tti_svc (UNIT *uptr)
{
int32 c;
sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return c;
if (c & SCPE_BREAK) /* break? */
tti_buf = RXDB_ERR | RXDB_FRM;
else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
uptr->pos = uptr->pos + 1;
tti_csr = tti_csr | CSR_DONE;
if (tti_csr & CSR_IE)
tti_int = 1;
return SCPE_OK;
}示例9: set_if3_connect
static t_stat set_if3_connect(UNIT *uptr, int32 val, char *cptr, void *desc)
{
if(uptr->flags & UNIT_DISABLE) {
TRACE_PRINT(ERROR_MSG, ("IF3[%d]: not enabled." NLP, uptr->u3));
return SCPE_OK;
}
if(val & UNIT_IF3_CONNECT) {
TRACE_PRINT((RXIRQ_MSG|TXIRQ_MSG), ("IF3[%d]: IRQ polling started..." NLP, uptr->u3));
sim_activate(uptr, 100000);
} else {
TRACE_PRINT((RXIRQ_MSG|TXIRQ_MSG), ("IF3[%d]: IRQ polling stopped." NLP, uptr->u3));
sim_cancel(uptr);
}
return (SCPE_OK);
}示例10: fei_svc
t_stat fei_svc (UNIT *uptr)
{
int32 temp;
sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll)));
/* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return temp;
if (temp & SCPE_BREAK) /* ignore break */
return SCPE_OK;
uptr->buf = temp & 0177;
uptr->pos = uptr->pos + 1;
M[FE_CTYIN] = uptr->buf | FE_CVALID; /* put char in mem */
apr_flg = apr_flg | APRF_CON; /* interrupt KS10 */
return SCPE_OK;
}示例11: clkio
int32 clkio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 015) /* only fnc 0,2 */
return IOBADFNC (dat);
CLR_INT (INT_CLK); /* reset ready */
if (fnc) /* fnc = 2? stop */
sim_cancel (&clk_unit);
else { /* fnc = 0? */
if (!sim_is_active (&clk_unit))
sim_activate (&clk_unit, /* activate */
sim_rtc_init (clk_unit.wait)); /* init calibr */
}
break;
case ioSKS: /* SKS */
if (fnc == 000) { /* clock skip !int */
if (!TST_INTREQ (INT_CLK))
return IOSKIP (dat);
}
else if ((fnc & 007) == 002) { /* mem parity? */
if (((fnc == 002) && !TST_INT (INT_MPE)) ||
((fnc == 012) && TST_INT (INT_MPE)))
return IOSKIP (dat);
}
else return IOBADFNC (dat); /* invalid fnc */
break;
case ioOTA: /* OTA */
if (fnc == 000) /* SMK */
dev_enb = dat;
else if (fnc == 010) { /* OTK */
C = (dat >> 15) & 1; /* set C */
if (cpu_unit.flags & UNIT_HSA) /* HSA included? */
dp = (dat >> 14) & 1; /* set dp */
if (cpu_unit.flags & UNIT_EXT) { /* ext opt? */
if (dat & 020000) { /* ext set? */
ext = 1; /* yes, set */
extoff_pending = 0;
}
else extoff_pending = 1; /* no, clr later */
}
sc = dat & 037; /* set sc */
}
else return IOBADFNC (dat);示例12: read_card
t_stat read_card (int32 ilnt, int32 mod)
{
int32 i, cbn, c1, c2, cbufsz;
t_stat r;
if (sim_is_active (&cdr_unit)) { /* busy? */
sim_cancel (&cdr_unit); /* cancel */
if ((r = cdr_svc (&cdr_unit))) /* process */
return r;
}
ind[IN_READ] = ind[IN_LST] = s1sel = s2sel = 0; /* default stacker */
cbn = ((ilnt == 2) || (ilnt == 5)) && (mod == BCD_C); /* col binary? */
cbufsz = (cbn)? 2 * CBUFSIZE: CBUFSIZE; /* buffer size */
for (i = 0; i < (2 * CBUFSIZE) + 1; i++) /* clear extended buf */
cdr_buf[i] = 0;
if ((cdr_unit.flags & UNIT_ATT) != 0) /* attached? */
r = cdr_read_file (cdr_buf, cbufsz); /* read from file */
else if ((cdr_unit.flags & UNIT_CONS) != 0) /* default to console? */
r = cdr_read_cons (cdr_buf, cbufsz); /* read from console */
else return SCPE_UNATT; /* else can't read */
if (r != SCPE_OK) /* read error? */
return r; /* can't read */
if (cbn) { /* column binary? */
for (i = 0; i < CDR_WIDTH; i++) {
if (conv_old) {
c1 = ascii2bcd (cdr_buf[i]);
c2 = ascii2bcd (cdr_buf[CDR_WIDTH + i]);
}
else {
c1 = ascii2bcd (cdr_buf[2 * i]);
c2 = ascii2bcd (cdr_buf[(2 * i) + 1]);
}
M[CD_CBUF1 + i] = (M[CD_CBUF1 + i] & WM) | c1;
M[CD_CBUF2 + i] = (M[CD_CBUF2 + i] & WM) | c2;
M[CDR_BUF + i] = colbin_to_bcd ((c1 << 6) | c2);
}
} /* end if col bin */
else { /* normal read */
for (i = 0; i < CDR_WIDTH; i++) { /* cvt to BCD */
c1 = ascii2bcd (cdr_buf[i]);
M[CDR_BUF + i] = (M[CDR_BUF + i] & WM) | c1;
}
}
M[CDR_BUF - 1] = 060; /* mem mark */
sim_activate (&cdr_unit, cdr_unit.wait); /* activate */
return SCPE_OK;
}示例13: ptp_nsi_cmd
/*
* Command codes
*
* xxxx01 Start punch.
* xxxx10 Stop punch.
* xx1xxx Start in Previous shift, else alpha.
* x1xxxx Graphics mode.
* 1xxxxx Punch blanks.
*/
void ptp_nsi_cmd(int dev, uint32 cmd) {
int i;
UNIT *uptr = NULL;
/* Find the unit from dev */
for (i = 0; i < ptp_dev.numunits; i++) {
if (GET_UADDR(ptp_unit[i].flags) == dev) {
uptr = &ptp_unit[i];
break;
}
}
/* Should not happen, but just in case */
if (uptr == NULL)
return;
/* Ignore this command if not a SI device */
if (SI_TYPE(uptr->flags))
return;
if (cmd & 02) {
if (uptr->CMD & BUSY)
uptr->CMD |= DISC;
return;
}
if (cmd & 01) {
if (uptr->CMD & BUSY || (uptr->flags & UNIT_ATT) == 0) {
uptr->STATUS |= OPAT;
chan_set_done(dev);
return;
}
if (cmd & 010)
uptr->CMD &= ALPHA_MODE;
else
uptr->CMD = ALPHA_MODE;
if (cmd & 020)
uptr->CMD |= BIN_MODE;
if ((cmd & 040) == 0)
uptr->CMD |= PUN_BLNK;
uptr->CMD |= BUSY;
uptr->STATUS = 0;
sim_activate(uptr, uptr->wait);
chan_clr_done(dev);
}
}示例14: dtc_cmd
/* Start off a terminal controller command */
t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
{
UNIT *uptr;
int ttu;
int buf;
uptr = &dtc_unit[0];
/* If unit disabled return error */
if (uptr->flags & UNIT_DIS)
return SCPE_NODEV;
if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT;
/* Check if drive is ready to recieve a command */
if ((uptr->CMD & DTC_RDY) == 0)
return SCPE_BUSY;
uptr->CMD = chan;
ttu = (*wc & DTCSTA_TTU) >> 5;
buf = (*wc & DTCSTA_BUF);
/* Set the Terminal unit. */
if (ttu == 0)
uptr->LINE = -1;
else {
uptr->LINE = buf + ((ttu-1) * 15);
}
if (*wc & DTCSTA_GM)
uptr->CMD |= DTC_IGNGM;
if (cmd & DTCSTA_READ)
uptr->CMD |= DTC_RD;
else if (cmd & DTCSTA_INHIBIT)
uptr->CMD |= DTC_INQ;
else
uptr->CMD |= DTC_WR;
if (cmd & DTCSTA_BINARY)
uptr->CMD |= DTC_BIN;
sim_debug(DEBUG_CMD, &dtc_dev, "Datacomm access %s %06o %d %04o\n",
(uptr->CMD & DTC_RD) ? "read" : ((uptr->CMD & DTC_INQ) ? "inq" :
((uptr->CMD & DTC_WR) ? "write" : "unknown")),
uptr->CMD, uptr->LINE, *wc);
sim_activate(uptr, 5000);
return SCPE_OK;
}示例15: ttix_reset
t_stat ttix_reset (DEVICE *dptr)
{
int32 ln, itto;
ttx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
if (ttix_unit.flags & UNIT_ATT) /* if attached, */
sim_activate (&ttix_unit, tmxr_poll); /* activate */
else sim_cancel (&ttix_unit); /* else stop */
for (ln = 0; ln < TTX_LINES; ln++) { /* for all lines */
ttix_buf[ln] = 0; /* clear buf, */
itto = (INT_TTI1 << ln); /* interrupt */
dev_done = dev_done & ~itto; /* clr done, int */
int_req = int_req & ~itto;
int_enable = int_enable | itto; /* set enable */
}
return SCPE_OK;
}