C++ setbits32函数代码示例

static void mpc866ads_fixup_scc_irda_pdata(struct platform_device *pdev,
					   int idx)
{
	immap_t *immap = (immap_t *) IMAP_ADDR;
	unsigned *bcsr_io;

	/* This is for IRDA devices only */
	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc:irda")))
		return;

	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));

	if (bcsr_io == NULL) {
		printk(KERN_CRIT "Could not remap BCSR1\n");
		return;
	}

	/* Enable the IRDA.
	 */
	clrbits32(bcsr_io,BCSR1_IRDAEN);
	iounmap(bcsr_io);

	/* Configure port A pins.
	 */
	setbits16(&immap->im_ioport.iop_papar, 0x000c);
	clrbits16(&immap->im_ioport.iop_padir, 0x000c);

	/* Configure Serial Interface clock routing.
	 * First, clear all SCC bits to zero, then set the ones we want.
	 */
	clrbits32(&immap->im_cpm.cp_sicr, 0x0000ff00);
	setbits32(&immap->im_cpm.cp_sicr, 0x00001200);
}

static void flipper_pic_unmask(struct irq_data *d)
{
	int irq = irqd_to_hwirq(d);
	void __iomem *io_base = irq_data_get_irq_chip_data(d);

	setbits32(io_base + FLIPPER_IMR, 1 << irq);
}

static int rcpm_suspend_enter(suspend_state_t state)
{
	int ret = 0;
	int result;

	switch (state) {
	case PM_SUSPEND_STANDBY:

		flush_dcache_L1();
		flush_backside_L2_cache();

		setbits32(&rcpm1_regs->powmgtcsr, RCPM_POWMGTCSR_SLP);
		/* At this point, the device is in sleep mode. */

		/* Upon resume, wait for SLP bit to be clear. */
		result = spin_event_timeout(
		  (in_be32(&rcpm1_regs->powmgtcsr) & RCPM_POWMGTCSR_SLP) == 0,
		  10000, 10);
		if (!result) {
			pr_err("%s: timeout waiting for SLP bit "
				"to be cleared\n", __func__);
			ret = -ETIMEDOUT;
		}
		break;

	default:
		ret = -EINVAL;

	}
	return ret;
}

static int cpm_uart_startup(struct uart_port *port)
{
	int retval;
	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;

	pr_debug("CPM uart[%d]:startup\n", port->line);

	/* If the port is not the console, make sure rx is disabled. */
	if (!(pinfo->flags & FLAG_CONSOLE)) {
		/* Disable UART rx */
		if (IS_SMC(pinfo)) {
			clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
			clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
		} else {
			clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
			clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
		}
		cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
	}
	/* Install interrupt handler. */
	retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
	if (retval)
		return retval;

	/* Startup rx-int */
	if (IS_SMC(pinfo)) {
		setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
		setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
	} else {
		setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
		setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
	}

	return 0;
}

static void __init init_ioports(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(km82xx_pins); i++) {
		const struct cpm_pin *pin = &km82xx_pins[i];
		cpm2_set_pin(pin->port, pin->pin, pin->flags);
	}

	cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
	cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_TX);
	cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RTX);
	cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9,  CPM_CLK_TX);
	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);

	/* Force USB FULL SPEED bit to '1' */
	setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
	/* clear USB_SLAVE */
	clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
}

static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
{
	int div;
	int pre_div = 2;

	clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
		  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);

	if (clock == 0)
		goto out;

	if (host->max_clk / 16 > clock) {
		for (; pre_div < 256; pre_div *= 2) {
			if (host->max_clk / pre_div < clock * 16)
				break;
		}
	}

	for (div = 1; div <= 16; div++) {
		if (host->max_clk / (div * pre_div) <= clock)
			break;
	}

	pre_div >>= 1;

	setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
		  ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
		  div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
	mdelay(100);
out:
	host->clock = clock;
}

/* Deferred service handler. Tasklet arg is simply the SNVS dev */
static void caam_secvio_dispatch(unsigned long indev)
{
	struct device *dev = (struct device *)indev;
	struct caam_drv_private_secvio *svpriv = dev_get_drvdata(dev);
	unsigned long flags, cause;
	int i;


	/*
	 * Capture the interrupt cause, using masked interrupts as
	 * identification. This only works if all are enabled; if
	  * this changes in the future, a "cause queue" will have to
	 * be built
	 */
	cause = rd_reg32(&svpriv->svregs->hp.secvio_int_ctl) &
			(HP_SECVIO_INTEN_SRC5 | HP_SECVIO_INTEN_SRC4 |
			 HP_SECVIO_INTEN_SRC3 | HP_SECVIO_INTEN_SRC2 |
			 HP_SECVIO_INTEN_SRC1 | HP_SECVIO_INTEN_SRC0);

	/* Look through causes, call each handler if exists */
	for (i = 0; i < MAX_SECVIO_SOURCES; i++)
		if (cause & (1 << i)) {
			spin_lock_irqsave(&svpriv->svlock, flags);
			svpriv->intsrc[i].handler(dev, i,
						  svpriv->intsrc[i].ext);
			spin_unlock_irqrestore(&svpriv->svlock, flags);
		};

	/* Re-enable now-serviced interrupts */
	setbits32(&svpriv->svregs->hp.secvio_int_ctl, cause);
}

static void setup_smc2_ioports(void)
{
        immap_t *immap = (immap_t *) IMAP_ADDR;
        unsigned *bcsr_io;
        unsigned int iobits = 0x00000c00;

        bcsr_io = ioremap(BCSR1, sizeof(unsigned long));

        if (bcsr_io == NULL) {
                printk(KERN_CRIT "Could not remap BCSR1\n");
                return;
        }
        clrbits32(bcsr_io,BCSR1_RS232EN_2);
        iounmap(bcsr_io);

#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
        setbits32(&immap->im_cpm.cp_pbpar, iobits);
        clrbits32(&immap->im_cpm.cp_pbdir, iobits);
        clrbits16(&immap->im_cpm.cp_pbodr, iobits);
#else
        setbits16(&immap->im_ioport.iop_papar, iobits);
        clrbits16(&immap->im_ioport.iop_padir, iobits);
        clrbits16(&immap->im_ioport.iop_paodr, iobits);
#endif
}

/* Top-level security violation interrupt */
static irqreturn_t caam_secvio_interrupt(int irq, void *snvsdev)
{
	struct device *dev = snvsdev;
	struct caam_drv_private_secvio *svpriv = dev_get_drvdata(dev);
	u32 irqstate;

	/* Check the HP secvio status register */
	irqstate = rd_reg32(&svpriv->svregs->hp.secvio_status) |
			    HP_SECVIOST_SECVIOMASK;

	if (!irqstate)
		return IRQ_NONE;

	/* Mask out one or more causes for deferred service */
	clrbits32(&svpriv->svregs->hp.secvio_int_ctl, irqstate);

	/* Now ACK causes */
	setbits32(&svpriv->svregs->hp.secvio_status, irqstate);

	/* And run deferred service */
	preempt_disable();
	tasklet_schedule(&svpriv->irqtask[smp_processor_id()]);
	preempt_enable();

	return IRQ_HANDLED;
}

static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
	unsigned long flags;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		setbits32(mm->regs + GPIO_ICR,
			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		clrbits32(mm->regs + GPIO_ICR,
			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

/**
 * pmc_enable_wake - enable OF device as wakeup event source
 * @ofdev: OF device affected
 * @state: PM state from which device will issue wakeup events
 * @enable: True to enable event generation; false to disable
 *
 * This enables the device as a wakeup event source, or disables it.
 *
 * RETURN VALUE:
 * 0 is returned on success
 * -EINVAL is returned if device is not supposed to wake up the system
 * Error code depending on the platform is returned if both the platform and
 * the native mechanism fail to enable the generation of wake-up events
 */
int pmc_enable_wake(struct of_device *ofdev, suspend_state_t state, bool enable)
{
	int ret = 0;
	struct device_node *clk_np;
	u32 *pmcdr_mask;

	if (enable && !device_may_wakeup(&ofdev->dev))
		return -EINVAL;

	clk_np = of_parse_phandle(ofdev->dev.of_node, "clk-handle", 0);
	if (!clk_np)
		return -EINVAL;

	pmcdr_mask = (u32 *)of_get_property(clk_np, "fsl,pmcdr-mask", NULL);
	if (!pmcdr_mask) {
		ret = -EINVAL;
		goto out;
	}

	/* clear to enable clock in low power mode */
	if (enable)
		clrbits32(&pmc_regs->pmcdr, *pmcdr_mask);
	else
		setbits32(&pmc_regs->pmcdr, *pmcdr_mask);

out:
	of_node_put(clk_np);
	return ret;
}

static void pcmcia_hw_setup(int slot, int enable)
{
    if (enable)
        clrbits32(&bcsr[1], BCSR1_PCCEN);
    else
        setbits32(&bcsr[1], BCSR1_PCCEN);
}

/**
 * pmc_enable_lossless - enable lossless ethernet in low power mode
 * @enable: True to enable event generation; false to disable
 */
void pmc_enable_lossless(int enable)
{
	if (enable && has_lossless)
		setbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
	else
		clrbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
}

static void __init mpc8272_ads_setup_arch(void)
{
	struct device_node *np;
	__be32 __iomem *bcsr;

	if (ppc_md.progress)
		ppc_md.progress("mpc8272_ads_setup_arch()", 0);

	cpm2_reset();

	np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
	if (!np) {
		printk(KERN_ERR "No bcsr in device tree\n");
		return;
	}

	bcsr = of_iomap(np, 0);
	of_node_put(np);
	if (!bcsr) {
		printk(KERN_ERR "Cannot map BCSR registers\n");
		return;
	}

#define BCSR1_FETHIEN		0x08000000
#define BCSR1_FETH_RST		0x04000000
#define BCSR1_RS232_EN1		0x02000000
#define BCSR1_RS232_EN2		0x01000000
#define BCSR3_USB_nEN		0x80000000
#define BCSR3_FETHIEN2		0x10000000
#define BCSR3_FETH2_RST		0x08000000

	clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
	setbits32(&bcsr[1], BCSR1_FETH_RST);

	clrbits32(&bcsr[3], BCSR3_FETHIEN2);
	setbits32(&bcsr[3], BCSR3_FETH2_RST);

	clrbits32(&bcsr[3], BCSR3_USB_nEN);

	iounmap(bcsr);

	init_ioports();
	pq2_init_pci();

	if (ppc_md.progress)
		ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
}

static void __init mpc85xx_mds_qe_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		np = of_find_node_by_name(NULL, "qe");
		if (!np)
			return;
	}

	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	qe_reset();
	of_node_put(np);

	np = of_find_node_by_name(NULL, "par_io");
	if (np) {
		struct device_node *ucc;

		par_io_init(np);
		of_node_put(np);

		for_each_node_by_name(ucc, "ucc")
			par_io_of_config(ucc);
	}

	mpc85xx_mds_reset_ucc_phys();

	if (machine_is(p1021_mds)) {

		struct ccsr_guts __iomem *guts;

		np = of_find_node_by_name(NULL, "global-utilities");
		if (np) {
			guts = of_iomap(np, 0);
			if (!guts)
				pr_err("mpc85xx-rdb: could not map global utilities register\n");
			else{
			/* P1021 has pins muxed for QE and other functions. To
			 * enable QE UEC mode, we need to set bit QE0 for UCC1
			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
			 * and QE12 for QE MII management signals in PMUXCR
			 * register.
			 */
				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
						  MPC85xx_PMUXCR_QE(3) |
						  MPC85xx_PMUXCR_QE(9) |
						  MPC85xx_PMUXCR_QE(12));
				iounmap(guts);
			}
			of_node_put(np);
		}

	}
}