C++ set_irq_chip函数代码示例

/*
 * This function should be called during kernel startup to initialize
 * the machine vector table.
 */
void __init init_IRQ(void)
{
    int i;

    /* set up the vectors */
    for (i = 72; i < 256; ++i)
        _ramvec[i] = (e_vector) bad_interrupt;

    _ramvec[32] = system_call;

    _ramvec[65] = (e_vector) inthandler1;
    _ramvec[66] = (e_vector) inthandler2;
    _ramvec[67] = (e_vector) inthandler3;
    _ramvec[68] = (e_vector) inthandler4;
    _ramvec[69] = (e_vector) inthandler5;
    _ramvec[70] = (e_vector) inthandler6;
    _ramvec[71] = (e_vector) inthandler7;

    IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */

    /* turn off all interrupts */
    IMR = ~0;

    for (i = 0; (i < NR_IRQS); i++) {
        set_irq_chip(i, &intc_irq_chip);
        set_irq_handler(i, handle_level_irq);
    }
}

static int __init mxc_pseudo_init(void)
{
	int i;

	/* disable the interrupt and clear the status */
	pseudo_irq_pending = 0;
	pseudo_irq_enable = 0;

	pr_info("3-Stack Pseudo interrupt rev=0.1v\n");

	for (i = MXC_PSEUDO_IO_BASE;
	     i < (MXC_PSEUDO_IO_BASE + 16); i++) {
		set_irq_chip(i, &pseudo_irq_chip);
		set_irq_handler(i, handle_simple_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN);
	set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler);

	/* Set and install PMIC IRQ handler */
	gpio_request(0, NULL);
	gpio_direction_input(0);

	set_irq_type(gpio_to_irq(0), IRQF_TRIGGER_RISING);
	if (request_irq(gpio_to_irq(0), mcu_irq_handler,
			0, "MCU_IRQ", 0)) {
		printk(KERN_ERR "mcu request irq failed\n");
		return -1;
	}
	return 0;
}

void __init ts4800_init_mux_irq(void)
{
   int n;
   volatile unsigned long x;
   volatile unsigned long *iomuxregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x000A8000);
   gpioregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x00088000);

   FPGA_REG(FPGA_IRQ_MASK_OFFSET) = 0xFFFF;  /* mask all */

    /*
    * On the TS-4800, the FPGA interrupt is connected to EIM_D27 on
    * the MX515. This pin must be configured as a GPIO pin, by writing
    * 001b to the MUX_MODE bits of the IOMUXC_SW_MUX_CTL_PAD_EIM_D27
    * register.  Doing so makes this pin EIM_GPIO2_9.
    */
   iomuxregs[0x88 / 4] = 1;

   gpioregs[0x18 / 4] = (1<<9);              // clr status for irq 169

   for(n=272; n < 280; n++)   {
      set_irq_chip(n, &muxed_irq_chip);
      set_irq_handler(n, handle_simple_irq);
      set_irq_flags(n, IRQF_VALID);
   }

   /* Install mux handler on GPIO2_9, which is IRQ #169 */
   set_irq_chained_handler(169, mux_irq_handler);

}

int sapphire_init_gpio(void)
{
	int i;
	if (!machine_is_sapphire())
		return 0;

	DBG("%d,%d\r\n",SAPPHIRE_INT_START, SAPPHIRE_INT_END);
	DBG("NR_MSM_IRQS=%d, NR_GPIO_IRQS=%d\r\n", NR_MSM_IRQS, NR_GPIO_IRQS);
	for(i = SAPPHIRE_INT_START; i <= SAPPHIRE_INT_END; i++) {
		set_irq_chip(i, &sapphire_gpio_irq_chip);
		set_irq_handler(i, handle_edge_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	register_gpio_chip(&sapphire_gpio_chip);
	register_gpio_chip(&sapphire_h2w_gpio_chip);

	/*setup CPLD INT connecting to SOC's gpio 17 */
	set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
	set_irq_chained_handler(MSM_GPIO_TO_INT(17), sapphire_gpio_irq_handler);
	set_irq_wake(MSM_GPIO_TO_INT(17), 1);

	if(sysdev_class_register(&sapphire_sysdev_class) == 0)
		sysdev_register(&sapphire_irq_device);

	return 0;
}

void __init omap_init_irq(void)
{
	unsigned long nr_irqs = 0;
	unsigned int nr_banks = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		if (cpu_is_omap24xx()) {
			bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE);
		}
		if (cpu_is_omap34xx()) {
			bank->base_reg = VA_IC_BASE;
		}
		omap_irq_bank_init_one(bank);

		nr_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");

	for (i = 0; i < nr_irqs; i++) {
		set_irq_chip(i, &omap_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
}

/*
 * This function initializes the AVIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
void __init mxc_init_irq(void)
{
	int i;
	u32 reg;

	/* put the AVIC into the reset value with
	 * all interrupts disabled
	 */
	__raw_writel(0, AVIC_INTCNTL);
	__raw_writel(0x1f, AVIC_NIMASK);

	/* disable all interrupts */
	__raw_writel(0, AVIC_INTENABLEH);
	__raw_writel(0, AVIC_INTENABLEL);

	/* all IRQ no FIQ */
	__raw_writel(0, AVIC_INTTYPEH);
	__raw_writel(0, AVIC_INTTYPEL);
	for (i = 0; i < MXC_MAX_INT_LINES; i++) {
		set_irq_chip(i, &mxc_avic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	/* Set WDOG2's interrupt the highest priority level (bit 28-31) */
	reg = __raw_readl(AVIC_NIPRIORITY6);
	reg |= (0xF << 28);
	__raw_writel(reg, AVIC_NIPRIORITY6);

	/* init architectures chained interrupt handler */
	mxc_register_gpios();

	printk(KERN_INFO "MXC IRQ initialized\n");
}

void __init epxa10db_init_irq(void)
{
	unsigned int i;
	
	request_resource(&iomem_resource, &irq_resource);

	/*
	 * This bit sets up the interrupt controller using 
	 * the 6 PLD interrupts mode (the default) each 
	 * irqs is assigned a priority which is the same
	 * as its interrupt number. This scheme is used because 
	 * its easy, but you may want to change it depending
	 * on the contents of your PLD
	 */

	writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
	for (i = 0; i < NR_IRQS; i++){
		writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
		set_irq_chip(i,&epxa_irq_chip);
		set_irq_handler(i,do_level_IRQ);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	/* Disable all interrupts */
	writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));

}

void __init ixp23xx_init_irq(void)
{
    int irq;

    /* Route everything to IRQ */
    *IXP23XX_INTR_SEL1 = 0x0;
    *IXP23XX_INTR_SEL2 = 0x0;
    *IXP23XX_INTR_SEL3 = 0x0;
    *IXP23XX_INTR_SEL4 = 0x0;

    /* Mask all sources */
    *IXP23XX_INTR_EN1 = 0x0;
    *IXP23XX_INTR_EN2 = 0x0;
    *IXP23XX_INTR_EN3 = 0x0;
    *IXP23XX_INTR_EN4 = 0x0;

    /*
     * Configure all IRQs for level-sensitive operation
     */
    for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
        ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
    }

    for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
        set_irq_chip(irq, &ixp23xx_pci_irq_chip);
        set_irq_handler(irq, handle_level_irq);
        set_irq_flags(irq, IRQF_VALID);
    }

    set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
}

void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
			  unsigned int irq_start)
{
	unsigned int max_irq;
	unsigned int i;

	if (gic_nr >= MAX_GIC_NR)
		BUG();

	gic_data[gic_nr].dist_base = base;
	gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;

	max_irq = _gic_dist_init(gic_nr);
	gic_data[gic_nr].max_irq = max_irq;

	/*
	 * Setup the Linux IRQ subsystem.
	 */
	for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
		set_irq_chip(i, &gic_chip);
		set_irq_chip_data(i, &gic_data[gic_nr]);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	writel(1, base + GIC_DIST_CTRL);
}

static __init int bast_irq_init(void)
{
	unsigned int i;

	if (machine_is_bast()) {
		printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");

		/* zap all the IRQs */

		__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);

		set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);

		/* register our IRQs */

		for (i = 0; i < 4; i++) {
			unsigned int irqno = bast_pc104_irqs[i];

			set_irq_chip(irqno, &bast_pc104_chip);
			set_irq_handler(irqno, handle_level_irq);
			set_irq_flags(irqno, IRQF_VALID);
		}
	}

	return 0;
}

void __init s3c3410_init_irq(void)
{
        int irq;

	for (irq = 0; irq < NR_IRQS; irq++) {
		set_irq_chip(irq, &s3c3410_chip);
		set_irq_handler(irq, do_level_IRQ);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/* mask and disable all further interrupts */
	outl(0x00000000, S3C3410X_INTMSK);

	/* set all to IRQ mode, not FIQ */
	outl(0x00000000, S3C3410X_INTMOD);

	/* Clear Intrerrupt pending register	*/
	outl(0x00000000, S3C3410X_INTPND);

	/*
	 * enable the gloabal interrupt flag, this should be
	 * safe now, all sources are masked out and acknowledged
	 */
	outb(inb(S3C3410X_SYSCON) | S3C3410X_SYSCON_GIE, S3C3410X_SYSCON);
}

static int __init msm_init_gpio(void)
{
	int i, j = 0;

	for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
		if (i - FIRST_GPIO_IRQ > msm_gpio_chips[j].chip.end) {
			if (j < ARRAY_SIZE(msm_gpio_chips) - 1)
				j++;
		}
		set_irq_chip_data(i, &msm_gpio_chips[j]);
		set_irq_chip(i, &msm_gpio_irq_chip);
		set_irq_handler(i, handle_edge_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
		writel(0, msm_gpio_chips[i].regs.int_en);
		register_gpio_chip(&msm_gpio_chips[i].chip);
	}

	set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
	set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
	set_irq_wake(INT_GPIO_GROUP1, 1);
	set_irq_wake(INT_GPIO_GROUP2, 2);
	return 0;
}

void __init msm_init_irq(void)
{
	unsigned n;

	/* select level interrupts */
	writel(0, VIC_INT_TYPE0);
	writel(0, VIC_INT_TYPE1);

	/* select highlevel interrupts */
	writel(0, VIC_INT_POLARITY0);
	writel(0, VIC_INT_POLARITY1);

	/* select IRQ for all INTs */
	writel(0, VIC_INT_SELECT0);
	writel(0, VIC_INT_SELECT1);

	/* disable all INTs */
	writel(0, VIC_INT_EN0);
	writel(0, VIC_INT_EN1);

	/* don't use 1136 vic */
	writel(0, VIC_CONFIG);

	/* enable interrupt controller */
	writel(1, VIC_INT_MASTEREN);

	for (n = 0; n < NR_MSM_IRQS; n++) {
		set_irq_chip(n, &msm_irq_chip);
		set_irq_handler(n, handle_level_irq);
		set_irq_flags(n, IRQF_VALID);
	}
}

void __init kirkwood_init_irq(void)
{
	int i;

	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));

	/*
	 * Mask and clear GPIO IRQ interrupts.
	 */
	writel(0, GPIO_LEVEL_MASK(0));
	writel(0, GPIO_EDGE_MASK(0));
	writel(0, GPIO_EDGE_CAUSE(0));
	writel(0, GPIO_LEVEL_MASK(32));
	writel(0, GPIO_EDGE_MASK(32));
	writel(0, GPIO_EDGE_CAUSE(32));

	for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
		set_irq_chip(i, &orion_gpio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		irq_desc[i].status |= IRQ_LEVEL;
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
}

static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
			    irq_hw_number_t hw)
{
	get_irq_desc(virq)->status |= IRQ_LEVEL;
	set_irq_chip(virq, &m82xx_pci_ic);
	return 0;
}