当前位置: 首页>>代码示例>>C++>>正文

C++ set_c0_status函数代码示例

本文整理汇总了C++中set_c0_status函数的典型用法代码示例。如果您正苦于以下问题：C++ set_c0_status函数的具体用法？C++ set_c0_status怎么用？C++ set_c0_status使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。


在下文中一共展示了set_c0_status函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。

示例1: enable_ev64120_irq

static void enable_ev64120_irq(unsigned int irq_nr)
{
	if (irq_nr >= 8)	// All PCI interrupts are on line 5 or 2
		set_c0_status(9 << 10);
	else
		set_c0_status(1 << (irq_nr + 8));
}
开发者ID:ivucica，项目名称:linux，代码行数:7，代码来源:irq.c

示例2: enable_brcm_irq

static void
enable_brcm_irq(unsigned int irq)
{
	if (irq < 8)
		set_c0_status(1 << (irq + 8));
	else
		set_c0_status(IE_IRQ0);
}
开发者ID:Cribstone，项目名称:linino，代码行数:8，代码来源:irq.c

示例3: enable_sead_irq

void enable_sead_irq(unsigned int irq_nr)
{
	if (irq_nr == SEADINT_UART0)
		set_c0_status(0x00000400);
	else
		if (irq_nr == SEADINT_UART1)
			set_c0_status(0x00000800);
}
开发者ID:sarnobat，项目名称:knoppix，代码行数:8，代码来源:sead_int.c

示例4: arch_init_irq

void __init arch_init_irq(void)
{
	int i;
	unsigned int gic_rev;

	mips_cpu_irq_init();

	if (cpu_has_vint)
		set_vi_handler(cp0_compare_irq, mips_timer_dispatch);

	if (gcmp_present) {
		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
		gic_present = 1;
	}

	if (gic_present) {
#if defined (CONFIG_MIPS_GIC_IPI)
		gic_call_int_base = GIC_IPI_CALL_VPE0;
		gic_resched_int_base = GIC_IPI_RESCHED_VPE0;
		fill_ipi_map();
#endif
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);

		GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
		printk("MIPS GIC RevID: %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);

		if (cpu_has_vint) {
			pr_info("Setting up vectored interrupts\n");
			set_vi_handler(2 + GIC_CPU_INT0, gic_irq_dispatch);	// CPU
#if defined (CONFIG_MIPS_GIC_IPI)
			set_vi_handler(2 + GIC_CPU_INT1, gic_irq_dispatch);	// IPI resched
			set_vi_handler(2 + GIC_CPU_INT2, gic_irq_dispatch);	// IPI call
#endif
			set_vi_handler(2 + GIC_CPU_INT3, gic_irq_dispatch);	// FE
			set_vi_handler(2 + GIC_CPU_INT4, gic_irq_dispatch);	// PCIe
		}

#if defined (CONFIG_MIPS_GIC_IPI)
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2 |
			      STATUSF_IP4 | STATUSF_IP3);
		
		/* setup ipi interrupts */
		for (i = 0; i < nr_cpu_ids; i++) {
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
		}
#else
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
		/* set hardware irq, mapped to GIC shared (skip 0, 1, 2, 5, 7) */
		for (i = 3; i <= 31; i++) {
			if (i != 5 && i != 7)
				irq_set_handler(MIPS_GIC_IRQ_BASE + i, handle_level_irq);
		}
		
	} else {
开发者ID:andy-padavan，项目名称:rt-n56u，代码行数:57，代码来源:irq-gic.c

示例5: enable_ev64120_irq

static void enable_ev64120_irq(unsigned int irq_nr)
{
	unsigned long flags;

	local_irq_save(flags);
	if (irq_nr >= 8)	// All PCI interrupts are on line 5 or 2
		set_c0_status(9 << 10);
	else
		set_c0_status(1 << (irq_nr + 8));
	local_irq_restore(flags);
}
开发者ID:BackupTheBerlios，项目名称:arp2-svn，代码行数:11，代码来源:irq.c

示例6: brcm_mips_int6_enable

/*
 * IRQ6 functions
 */
static void brcm_mips_int6_enable(unsigned int irq)
{
        set_c0_status(STATUSF_IP6);
        INTC->extIrqMask |= (EXTIRQ4_EN);

        /* enable mips int2 for DMA ints. */
        set_c0_status(STATUSF_IP2);

        /* enable ISB DMA EBI RCV (DMA channel 1) interrupt for DMA receive */
        INTC->IrqMask |= DMA_IRQ;
        DMA_CHAN[EBI_RX_CHAN].intMask |= DMA_BUFF_DONE;

        /* enable EBI TX interrupt. */
        INTC->IrqMask |= EBI_TX_IRQ;
}
开发者ID:foxsat-hdr，项目名称:linux-kernel，代码行数:18，代码来源:irq.c

示例7: init_IRQ

void __init init_IRQ(void)
{
  int i;

  DANUBE_INT_DMSG("init_IRQ\n");

  board_be_handler = &danube_be_handler;

  init_generic_irq();

  /* mask all interrupt sources */
  *DANUBE_ICU_IM0_IER = 0;
  *DANUBE_ICU_IM1_IER = 0;
  *DANUBE_ICU_IM2_IER = 0;
  *DANUBE_ICU_IM3_IER = 0;
  *DANUBE_ICU_IM4_IER = 0;


  /* Now safe to set the exception vector. */
  set_except_vector(0, mipsIRQ);

  for (i = 0; i <= INT_NUM_IM4_IRL31; i++) {
    irq_desc[i].status	= IRQ_DISABLED;
    irq_desc[i].action	= 0;
    irq_desc[i].depth	= 1;
    irq_desc[i].handler	= &danube_irq_type;
  }

  set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);

#ifdef CONFIG_KGDB
  set_debug_traps();
  breakpoint();
#endif
}
开发者ID:jameshilliard，项目名称:core1-tar4F9632C8CCCE，代码行数:35，代码来源:interrupt.c

示例8: octeon_unmask_irq

static void octeon_unmask_irq(unsigned int irq)
{
    unsigned long flags;
    spin_lock_irqsave(&octeon_irq_lock, flags);
    if (irq < 8)
    {
        /* Core local interrupts, irq 0-7 */
        clear_c0_cause(0x100 << irq);
        set_c0_status(0x100 << irq);
    }
    else if (irq<72)
    {
        /* Interrupts from the CIU, irq 8-71 */
        const uint64_t coreid = octeon_get_core_num();
        uint64_t bit = (irq - 8) & 0x3f;    /* Bit 0-63 of EN0 */
        uint64_t en0 = octeon_read_csr(OCTEON_CIU_INTX_EN0(coreid*2));
        en0 |= 1ull<<bit;
        octeon_write_csr(OCTEON_CIU_INTX_EN0(coreid*2), en0);
    }
    else if (irq<88)
    {
        /* Interrupts from the master 8259, irq 80-87 */
        outb(inb(0x21) & ~(1<<(irq-80)), 0x21);
    }
    else if (irq<96)
    {
        /* Interrupts from the slave 8259, irq 88-95 */
        outb(inb(0xa1) & ~(1<<(irq-88)), 0xa1);
    }
    spin_unlock_irqrestore(&octeon_irq_lock, flags);
}
开发者ID:jameshilliard，项目名称:actiontec_opensrc_mi424wr-rev-e-f_fw-20-10-7-5，代码行数:31，代码来源:irq-octeon.c

示例9: bcm63xx_external_irq_startup

static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
{
	set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
	irq_enable_hazard();
	bcm63xx_external_irq_unmask(d);
	return 0;
}
开发者ID:08opt，项目名称:linux，代码行数:7，代码来源:irq.c

示例10: brcm_mips_int2_enable

static void brcm_mips_int2_enable(unsigned int irq)
{
	set_c0_status(STATUSF_IP2);
#if 0  /* JPF */
	switch(irq)
	{
		case BCM_LINUX_IDE0_IRQ:
			INTC->IrqMask |= (IDE0_IRQ);
		break;

		case BCM_LINUX_IDE1_IRQ:
			INTC->IrqMask |= (IDE1_IRQ);
		break;

		case BCM_LINUX_USB_HOST1_IRQ:
			INTC->IrqMask |= (USB_HOST1_IRQ);
		break;

		case BCM_LINUX_UARTA_IRQ:
			// This has to change depending on the console tty device we choose to use 
			// (defined in cmdline).
			INTC->IrqMask |= UPG_IRQ;
			UPG_INTC->irqen_l |= UPG_UA_IRQ;
		break;

		default:
		break;
	}
#endif
}
开发者ID:foxsat-hdr，项目名称:linux-kernel，代码行数:30，代码来源:irq.c

示例11: enable_brcm_irq

void enable_brcm_irq(unsigned int irq)
{
	unsigned long flags;
	int i, bit;

	if (irq <= MIPS_TIMER_INT)
	{
		if (irq == MIPS_TIMER_INT)
			return;
		set_c0_status(1 << (STATUSB_IP0 + irq - INTERRUPT_ID_SOFTWARE_0));
		return;
	}
	for (i = 0; i < (sizeof(irq_table)/sizeof(irq_ctl *)); i++)
	{
		if (irq >= irq_table[i]->vstart && irq < irq_table[i]->vend)
		{
			bit = irq - irq_table[i]->vstart;
			spin_lock_irqsave(&brcm_irqlock, flags);
			*(irq_table[i]->enable) |= (1 << bit);
			if (irq_table[i]->lower_level)
			{
				*(irq_table[i]->lower_level->enable) |= 1 << irq_table[i]->lower_level_bit;
			}
			spin_unlock_irqrestore(&brcm_irqlock, flags);
			return;
		}
	}
	printk("ERROR in %s: unable to enable irq %d\n", __func__, irq);
}
开发者ID:tch-opensrc，项目名称:TC72XX_LxG1.0.10mp5_OpenSrc，代码行数:29，代码来源:irq.c

示例12: per_cpu_init

void __cpuinit per_cpu_init(void)
{
	int cpu = smp_processor_id();
	int slice = LOCAL_HUB_L(PI_CPU_NUM);
	cnodeid_t cnode = get_compact_nodeid();
	struct hub_data *hub = hub_data(cnode);
	struct slice_data *si = hub->slice + slice;
	int i;

	if (test_and_set_bit(slice, &hub->slice_map))
		return;

	clear_c0_status(ST0_IM);

	per_hub_init(cnode);

	for (i = 0; i < LEVELS_PER_SLICE; i++)
		si->level_to_irq[i] = -1;

	/*
                                                                   
             
  */
	cpu_data[cpu].data = si;

	cpu_time_init();
	install_ipi();

	/*                                                         */
	install_cpu_nmi_handler(cputoslice(cpu));

	set_c0_status(SRB_DEV0 | SRB_DEV1);
}
开发者ID:romanbb，项目名称:android_kernel_lge_d851，代码行数:33，代码来源:ip27-init.c

示例13: arch_init_irq

void __init arch_init_irq(void)
{
	int i;
	unsigned long cp0_status;
	au1xxx_irq_map_t *imp;
	extern au1xxx_irq_map_t au1xxx_irq_map[];
	extern au1xxx_irq_map_t au1xxx_ic0_map[];
	extern int au1xxx_nr_irqs;
	extern int au1xxx_ic0_nr_irqs;

	cp0_status = read_c0_status();
	set_except_vector(0, au1000_IRQ);

	/* Initialize interrupt controllers to a safe state.
	*/
	au_writel(0xffffffff, IC0_CFG0CLR);
	au_writel(0xffffffff, IC0_CFG1CLR);
	au_writel(0xffffffff, IC0_CFG2CLR);
	au_writel(0xffffffff, IC0_MASKCLR);
	au_writel(0xffffffff, IC0_ASSIGNSET);
	au_writel(0xffffffff, IC0_WAKECLR);
	au_writel(0xffffffff, IC0_SRCSET);
	au_writel(0xffffffff, IC0_FALLINGCLR);
	au_writel(0xffffffff, IC0_RISINGCLR);
	au_writel(0x00000000, IC0_TESTBIT);

	au_writel(0xffffffff, IC1_CFG0CLR);
	au_writel(0xffffffff, IC1_CFG1CLR);
	au_writel(0xffffffff, IC1_CFG2CLR);
	au_writel(0xffffffff, IC1_MASKCLR);
	au_writel(0xffffffff, IC1_ASSIGNSET);
	au_writel(0xffffffff, IC1_WAKECLR);
	au_writel(0xffffffff, IC1_SRCSET);
	au_writel(0xffffffff, IC1_FALLINGCLR);
	au_writel(0xffffffff, IC1_RISINGCLR);
	au_writel(0x00000000, IC1_TESTBIT);

	/* Initialize IC0, which is fixed per processor.
	*/
	imp = au1xxx_ic0_map;
	for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	/* Now set up the irq mapping for the board.
	*/
	imp = au1xxx_irq_map;
	for (i=0; i<au1xxx_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	set_c0_status(ALLINTS);

	/* Board specific IRQ initialization.
	*/
	if (board_init_irq)
		(*board_init_irq)();
}
开发者ID:KrisChaplin，项目名称:LRT2x4_v1.0.2.06_GPL_source，代码行数:60，代码来源:irq.c

示例14: ar7_irq_init

static void __init ar7_irq_init(int base)
{
	int i;
	/*
	 * Disable interrupts and clear pending
	 */
	writel(0xffffffff, REG(ECR_OFFSET(0)));
	writel(0xff, REG(ECR_OFFSET(32)));
	writel(0xffffffff, REG(SEC_ECR_OFFSET));
	writel(0xffffffff, REG(CR_OFFSET(0)));
	writel(0xff, REG(CR_OFFSET(32)));
	writel(0xffffffff, REG(SEC_CR_OFFSET));

	ar7_irq_base = base;

	for (i = 0; i < 40; i++) {
		writel(i, REG(CHNL_OFFSET(i)));
		/* Primary IRQ's */
		set_irq_chip_and_handler(base + i, &ar7_irq_type,
					 handle_level_irq);
		/* Secondary IRQ's */
		if (i < 32)
			set_irq_chip_and_handler(base + i + 40,
						 &ar7_sec_irq_type,
						 handle_level_irq);
	}

	setup_irq(2, &ar7_cascade_action);
	setup_irq(ar7_irq_base, &ar7_cascade_action);
	set_c0_status(IE_IRQ0);
}
开发者ID:ANFS，项目名称:ANFS-kernel，代码行数:31，代码来源:irq.c

示例15: rs780e_init_irq

void rs780e_init_irq(void)
{

	/* Route the HT interrupt to Core0 INT1 */
	INT_router_regs_HT1_int0 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int1 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int2 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int3 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int4 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int5 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int6 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int7 = 0x20 | (1 << phy_core_id[0]);
	/* Enable the all HT interrupt */
	HT_irq_enable_reg0 = 0x0000ffff;
	HT_irq_enable_reg1 = 0x00000000;
	HT_irq_enable_reg2 = 0x00000000;
	HT_irq_enable_reg3 = 0x00000000;
	HT_irq_enable_reg4 = 0x00000000;
	HT_irq_enable_reg5 = 0x00000000;
	HT_irq_enable_reg6 = 0x00000000;
	HT_irq_enable_reg7 = 0x00000000;

	/* Enable the IO interrupt controller */ 
	IO_control_regs_Intenset = IO_control_regs_Inten | (0xffff << 16);
	prom_printf("the new IO inten is %x\n", IO_control_regs_Inten);

	/* Sets the first-level interrupt dispatcher. */
	mips_cpu_irq_init();	

#ifdef CONFIG_I8259
	init_i8259_irqs();
#endif
	set_c0_status(STATUSF_IP6);
	mach_ip3 = dispatch_ht_irq;
}
开发者ID:laitianli，项目名称:loongson-linux-2.6.36-3_mips，代码行数:35，代码来源:rs780e-irq.c


注：本文中的set_c0_status函数示例由纯净天空整理自Github/MSDocs等开源代码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。