本文整理汇总了C++中sdhci_writeb函数的典型用法代码示例。如果您正苦于以下问题:C++ sdhci_writeb函数的具体用法?C++ sdhci_writeb怎么用?C++ sdhci_writeb使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了sdhci_writeb函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: sdhci_set_power
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr = 0;
if (power != (unsigned short)-1) {
switch (1 << power) {
case MMC_VDD_165_195:
pwr = SDHCI_POWER_180;
break;
case MMC_VDD_29_30:
case MMC_VDD_30_31:
pwr = SDHCI_POWER_300;
break;
case MMC_VDD_32_33:
case MMC_VDD_33_34:
pwr = SDHCI_POWER_330;
break;
}
}
if (pwr == 0) {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
return;
}
if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
示例2: tegra_sdhci_enable_clock
static void tegra_sdhci_enable_clock(struct tegra_sdhci_host *host, int enable)
{
if (enable && !host->clk_enabled) {
clk_enable(host->clk);
sdhci_writeb(host->sdhci, 1, SDHCI_VENDOR_CLOCK_CNTRL);
host->clk_enabled = 1;
} else if (!enable && host->clk_enabled) {
sdhci_writeb(host->sdhci, 0, SDHCI_VENDOR_CLOCK_CNTRL);
clk_disable(host->clk);
host->clk_enabled = 0;
}
}
示例3: sdhci_restore_regs
static void sdhci_restore_regs(struct sdhci_host *host)
{
if (!strcmp("Spread SDIO host1", host->hw_name)){
sdhci_writel(host, host_addr, SDHCI_DMA_ADDRESS);
sdhci_writew(host, host_blk_size, SDHCI_BLOCK_SIZE);
sdhci_writew(host, host_blk_cnt, SDHCI_BLOCK_COUNT);
sdhci_writel(host, host_arg, SDHCI_ARGUMENT);
sdhci_writew(host, host_tran_mode, SDHCI_TRANSFER_MODE);
sdhci_writeb(host, host_ctrl, SDHCI_HOST_CONTROL);
sdhci_writeb(host, host_power, SDHCI_POWER_CONTROL);
sdhci_writew(host, host_clk, SDHCI_CLOCK_CONTROL);
}
}
示例4: sdhci_set_ios
void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if (host->version >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if (host->version >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
示例5: sdhci_s3c_platform_bus_width
/**
* sdhci_s3c_platform_bus_width - support 8bit buswidth
* @host: The SDHCI host being queried
* @width: MMC_BUS_WIDTH_ macro for the bus width being requested
*
* We have 8-bit width support but is not a v3 controller.
* So we add platform_bus_width() and support 8bit width.
*/
static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
{
u8 ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
switch (width) {
case MMC_BUS_WIDTH_8:
ctrl |= SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
break;
case MMC_BUS_WIDTH_4:
ctrl |= SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
break;
default:
ctrl &= ~SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
break;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}
示例6: sdhci_s3c_platform_8bit_width
/**
* sdhci_s3c_platform_8bit_width - support 8bit buswidth
* @host: The SDHCI host being queried
* @width: MMC_BUS_WIDTH_ macro for the bus width being requested
*
* We have 8-bit width support but is not a v3 controller.
* So we add platform_8bit_width() and support 8bit width.
*/
static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
{
u8 ctrl;
struct sdhci_s3c *ourhost = to_s3c(host);
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
switch (width) {
case MMC_BUS_WIDTH_8:
ctrl |= SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
/* call cfg_gpio with 8bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 8);
break;
case MMC_BUS_WIDTH_4:
ctrl |= SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
/* call cfg_gpio with 4bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 4);
break;
default:
ctrl &= ~SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
/* call cfg_gpio with 1bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 1);
break;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}
示例7: sdhci_init
static int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = mmc->priv;
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
aligned_buffer = memalign(8, 512*1024);
if (!aligned_buffer) {
printf("%s: Aligned buffer alloc failed!!!\n",
__func__);
return -1;
}
}
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
if (host->quirks & SDHCI_QUIRK_NO_CD) {
#if defined(CONFIG_PIC32_SDHCI)
/* PIC32 SDHCI CD errata:
* - set CD_TEST and clear CD_TEST_INS bit
*/
sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
#else
unsigned int status;
sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
SDHCI_HOST_CONTROL);
status = sdhci_readl(host, SDHCI_PRESENT_STATE);
while ((!(status & SDHCI_CARD_PRESENT)) ||
(!(status & SDHCI_CARD_STATE_STABLE)) ||
(!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
status = sdhci_readl(host, SDHCI_PRESENT_STATE);
#endif
}
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
SDHCI_INT_ENABLE);
/* Mask all sdhci interrupt sources */
sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
return 0;
}
示例8: sdhci_transfer_data
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
bool transfer_done = false;
#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif
timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
pr_debug("%s: Error detected in status(0x%X)!\n",
__func__, stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
if (++block >= data->blocks) {
/* Keep looping until the SDHCI_INT_DATA_END is
* cleared, even if we finished sending all the
* blocks.
*/
transfer_done = true;
continue;
}
}
#ifdef CONFIG_MMC_SDHCI_SDMA
if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
if (timeout-- > 0)
udelay(10);
else {
printf("%s: Transfer data timeout\n", __func__);
return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
示例9: tegra_sdhci_resume
static int tegra_sdhci_resume(struct platform_device *pdev)
{
struct tegra_sdhci_host *host = platform_get_drvdata(pdev);
int ret;
#ifdef CONFIG_MACH_SAMSUNG_VARIATION_TEGRA
int i, present;
#endif
u8 pwr;
if (host->card_always_on && is_card_sdio(host->sdhci->mmc->card)) {
int ret = 0;
if (device_may_wakeup(&pdev->dev)) {
disable_irq_wake(host->sdhci->irq);
}
/* soft reset SD host controller and enable interrupts */
ret = tegra_sdhci_restore(host->sdhci);
if (ret) {
pr_err("%s: failed, error = %d\n", __func__, ret);
return ret;
}
mmiowb();
#ifdef CONFIG_MACH_SAMSUNG_VARIATION_TEGRA
for(i=0;i<20;i++){
present = sdhci_readl(host->sdhci, SDHCI_PRESENT_STATE);
if((present & SDHCI_CARD_PRESENT) == SDHCI_CARD_PRESENT)
break;
mdelay(5);
// printk(KERN_ERR "MMC : %s : 6(Card Presnet %x) : %d \n",mmc_hostname(host->sdhci->mmc),present,i);
}
#endif
host->sdhci->mmc->ops->set_ios(host->sdhci->mmc,
&host->sdhci->mmc->ios);
return 0;
}
tegra_sdhci_enable_clock(host, 1);
pwr = SDHCI_POWER_ON;
sdhci_writeb(host->sdhci, pwr, SDHCI_POWER_CONTROL);
host->sdhci->pwr = 0;
ret = sdhci_resume_host(host->sdhci);
if (ret)
pr_err("%s: failed, error = %d\n", __func__, ret);
return ret;
}
示例10: sdhci_reset
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
/* Wait max 100 ms */
timeout = 100;
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
printf("Reset 0x%x never completed.\n", (int)mask);
return;
}
timeout--;
udelay(1000);
}
}
示例11: sdhci_transfer_data
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif
timeout = 90000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
errorf("%s: Error detected in status(0x%X)!\n",
__func__, stat);
return -1;
}
if (stat & rdy) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
if (++block >= data->blocks)
break;
}
#ifdef CONFIG_MMC_SDMA
if (stat & SDHCI_INT_DMA_END) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
if (timeout-- > 0)
udelay(10);
else {
errorf("%s: Transfer data timeout\n", __func__);
return -1;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
示例12: bcm_kona_sd_reset
static int bcm_kona_sd_reset(struct sdio_dev *dev)
{
struct sdhci_host *host = dev->host;
unsigned int val;
#ifdef CONFIG_ARCH_CAPRI
unsigned int tries = 10000;
#endif
unsigned long timeout;
/* Reset host controller by setting 'Software Reset for All' */
sdhci_writeb(host, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
/* Wait for 100 ms max (100ms timeout is taken from sdhci.c) */
timeout = jiffies + msecs_to_jiffies(100);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
if (time_is_before_jiffies(timeout)) {
dev_err(dev->dev, "Error: sd host is in reset!!!\n");
return -EFAULT;
}
}
/* reset the host using the top level reset */
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
val |= KONA_SDHOST_RESET;
sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
do {
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
#ifdef CONFIG_ARCH_CAPRI
if (--tries <= 0)
break;
#endif
} while (0 == (val & KONA_SDHOST_RESET));
/* bring the host out of reset */
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
val &= ~KONA_SDHOST_RESET;
/* Back-to-Back register write needs a delay of 1ms
* at bootup (min 10uS)
*/
udelay(1000);
sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
return 0;
}
示例13: sdhci_set_ios
static int sdhci_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int sdhci_set_ios(struct mmc *mmc)
{
#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
(host->quirks & SDHCI_QUIRK_USE_WIDE8))
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
(host->quirks & SDHCI_QUIRK_USE_WIDE8))
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}
示例14: sdhci_set_ios
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
u32 ctrl;
struct sdhci_host *host = mmc_priv(mmc);
if (host->ops.set_control_reg) {
host->ops.set_control_reg(host);
}
if (ios->clock != host->clock) {
sdhci_set_clock(mmc, ios->clock);
}
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (ios->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if ((host->sdhci_version & SDHCI_SPEC_VER_MASK) >=
SDHCI_SPEC_300) {
ctrl |= SDHCI_CTRL_8BITBUS;
}
} else {
if ((host->sdhci_version & SDHCI_SPEC_VER_MASK) >=
SDHCI_SPEC_300) {
ctrl &= ~SDHCI_CTRL_8BITBUS;
}
if (ios->bus_width == 4) {
ctrl |= SDHCI_CTRL_4BITBUS;
} else {
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
}
if (ios->clock > 26000000) {
ctrl |= SDHCI_CTRL_HISPD;
} else {
ctrl &= ~SDHCI_CTRL_HISPD;
}
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) {
ctrl &= ~SDHCI_CTRL_HISPD;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
示例15: tegra_sdhci_reset_exit
static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_tegra *tegra_host = pltfm_host->priv;
const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
if (!(mask & SDHCI_RESET_ALL))
return;
/* Erratum: Enable SDHCI spec v3.00 support */
if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
u32 misc_ctrl;
misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
}
}