本文整理汇总了C++中sdhci_readb函数的典型用法代码示例。如果您正苦于以下问题:C++ sdhci_readb函数的具体用法?C++ sdhci_readb怎么用?C++ sdhci_readb使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了sdhci_readb函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: sdhci_save_regs
static void sdhci_save_regs(struct sdhci_host *host)
{
if (!strcmp("Spread SDIO host1", host->hw_name)){
host_addr = sdhci_readl(host, SDHCI_DMA_ADDRESS);
host_blk_size = sdhci_readw(host, SDHCI_BLOCK_SIZE);
host_blk_cnt = sdhci_readw(host, SDHCI_BLOCK_COUNT);
host_arg = sdhci_readl(host, SDHCI_ARGUMENT);
host_tran_mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
host_ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
host_power = sdhci_readb(host, SDHCI_POWER_CONTROL);
host_clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
}
}
示例2: sdhci_display_bus_width
static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr)
{
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
int bits;
uint8_t host_ctrl;
uint16_t host2;
const char *rate;
uint16_t timing;
/* Display the bus width */
host_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
host2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
timing = host2 & SDHCI_CTRL_UHS_MASK;
bits = 1;
if (host_ctrl & SDHCI_CTRL_8BITBUS)
bits = 8;
else if (host_ctrl & SDHCI_CTRL_4BITBUS)
bits = 4;
rate = "SDR";
if ((timing == SDHCI_CTRL_UHS_DDR50)
|| (timing == SDHCI_CTRL_HS400))
rate = "DDR";
sdhc_debug("SDHCI bus width: %d bit%s %s\n", bits,
(bits != 1) ? "s" : "", rate);
}
}
示例3: sdhci_set_ios
void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if (host->version >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if (host->version >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
示例4: tegra_sdhci_restore
static int tegra_sdhci_restore(struct sdhci_host *sdhost)
{
unsigned long timeout;
u8 mask = SDHCI_RESET_ALL;
sdhci_writeb(sdhost, mask, SDHCI_SOFTWARE_RESET);
sdhost->clock = 0;
/* Wait max 100 ms */
timeout = 100;
/* hw clears the bit when it's done */
while (sdhci_readb(sdhost, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
mmc_hostname(sdhost->mmc), (int)mask);
return -EIO;
}
timeout--;
mdelay(1);
}
tegra_sdhci_restore_interrupts(sdhost);
return 0;
}
示例5: sdhci_s3c_platform_bus_width
/**
* sdhci_s3c_platform_bus_width - support 8bit buswidth
* @host: The SDHCI host being queried
* @width: MMC_BUS_WIDTH_ macro for the bus width being requested
*
* We have 8-bit width support but is not a v3 controller.
* So we add platform_bus_width() and support 8bit width.
*/
static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
{
u8 ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
switch (width) {
case MMC_BUS_WIDTH_8:
ctrl |= SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
break;
case MMC_BUS_WIDTH_4:
ctrl |= SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
break;
default:
ctrl &= ~SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
break;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}
示例6: sdhci_s3c_platform_8bit_width
/**
* sdhci_s3c_platform_8bit_width - support 8bit buswidth
* @host: The SDHCI host being queried
* @width: MMC_BUS_WIDTH_ macro for the bus width being requested
*
* We have 8-bit width support but is not a v3 controller.
* So we add platform_8bit_width() and support 8bit width.
*/
static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
{
u8 ctrl;
struct sdhci_s3c *ourhost = to_s3c(host);
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
switch (width) {
case MMC_BUS_WIDTH_8:
ctrl |= SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
/* call cfg_gpio with 8bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 8);
break;
case MMC_BUS_WIDTH_4:
ctrl |= SDHCI_CTRL_4BITBUS;
ctrl &= ~SDHCI_CTRL_8BITBUS;
/* call cfg_gpio with 4bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 4);
break;
default:
ctrl &= ~SDHCI_CTRL_8BITBUS;
ctrl &= ~SDHCI_CTRL_4BITBUS;
/* call cfg_gpio with 1bit data bus */
if (ourhost->pdata->cfg_gpio)
ourhost->pdata->cfg_gpio(ourhost->pdev, 1);
break;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}
示例7: sdhci_dumpregs
void sdhci_dumpregs(struct sdhci_host *host)
{
int i = 0;
printf(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
printf(KERN_DEBUG DRIVER_NAME ":AHB CTRL 0x%08x\n", *((unsigned int*)0x20900200));
#if 1
for(i = 0; i < MAX_DUMP_NUM; i++){
printf(KERN_DEBUG DRIVER_NAME ": address 0x%08x | value 0x%08x\n", host->ioaddr + i*4, sdhci_readl(host, i*4));
}
#endif
printf(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
sdhci_readl(host, SDHCI_DMA_ADDRESS),
sdhci_readw(host, SDHCI_HOST_VERSION));
printf(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
sdhci_readw(host, SDHCI_BLOCK_SIZE),
sdhci_readw(host, SDHCI_BLOCK_COUNT));
printf(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
sdhci_readl(host, SDHCI_ARGUMENT),
sdhci_readw(host, SDHCI_TRANSFER_MODE));
printf(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
sdhci_readl(host, SDHCI_PRESENT_STATE),
sdhci_readb(host, SDHCI_HOST_CONTROL));
printf(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
sdhci_readb(host, SDHCI_POWER_CONTROL),
sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
printf(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
sdhci_readw(host, SDHCI_CLOCK_CONTROL));
printf(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
sdhci_readl(host, SDHCI_INT_STATUS));
printf(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
sdhci_readl(host, SDHCI_INT_ENABLE),
sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
printf(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
sdhci_readw(host, SDHCI_ACMD12_ERR),
sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
printf(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
sdhci_readl(host, SDHCI_CAPABILITIES),
sdhci_readl(host, SDHCI_MAX_CURRENT));
printf(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
readl(host->ioaddr + SDHCI_ADMA_ERROR),
readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
printf(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
}
示例8: init_kona_mmc_core
static int init_kona_mmc_core(struct sdhci_host *host)
{
unsigned int mask;
unsigned int timeout;
if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
printf("%s: sd host controller reset error\n", __func__);
return -EBUSY;
}
/* For kona a hardware reset before anything else. */
mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
/* Wait max 100 ms */
timeout = 1000;
do {
if (timeout == 0) {
printf("%s: reset timeout error\n", __func__);
return -ETIMEDOUT;
}
timeout--;
udelay(100);
} while (0 ==
(sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
SDHCI_CORECTRL_RESET));
/* Clear the reset bit. */
mask = mask & ~SDHCI_CORECTRL_RESET;
sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
/* Enable AHB clock */
mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
/* Enable interrupts */
sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
/* Make sure Card is detected in controller */
mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
/* Wait max 100 ms */
timeout = 1000;
while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
if (timeout == 0) {
printf("%s: CARD DETECT timeout error\n", __func__);
return -ETIMEDOUT;
}
timeout--;
udelay(100);
}
return 0;
}
示例9: sdhci_transfer_data
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
bool transfer_done = false;
#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif
timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
pr_debug("%s: Error detected in status(0x%X)!\n",
__func__, stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
if (++block >= data->blocks) {
/* Keep looping until the SDHCI_INT_DATA_END is
* cleared, even if we finished sending all the
* blocks.
*/
transfer_done = true;
continue;
}
}
#ifdef CONFIG_MMC_SDHCI_SDMA
if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
if (timeout-- > 0)
udelay(10);
else {
printf("%s: Transfer data timeout\n", __func__);
return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
示例10: sdhci_cmd_done
static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
int i;
if (cmd->resp_type & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0; i < 4; i++) {
cmd->response[i] = sdhci_readl(host,
SDHCI_RESPONSE + (3-i)*4) << 8;
if (i != 3)
cmd->response[i] |= sdhci_readb(host,
SDHCI_RESPONSE + (3-i)*4-1);
}
} else {
cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
}
}
示例11: sdhci_reset
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
/* Wait max 100 ms */
timeout = 100;
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
printf("Reset 0x%x never completed.\n", (int)mask);
return;
}
timeout--;
udelay(1000);
}
}
示例12: sdhci_transfer_data
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
#ifdef CONFIG_MMC_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif
timeout = 90000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
errorf("%s: Error detected in status(0x%X)!\n",
__func__, stat);
return -1;
}
if (stat & rdy) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
if (++block >= data->blocks)
break;
}
#ifdef CONFIG_MMC_SDMA
if (stat & SDHCI_INT_DMA_END) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
if (timeout-- > 0)
udelay(10);
else {
errorf("%s: Transfer data timeout\n", __func__);
return -1;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
示例13: bcm_kona_sd_reset
static int bcm_kona_sd_reset(struct sdio_dev *dev)
{
struct sdhci_host *host = dev->host;
unsigned int val;
#ifdef CONFIG_ARCH_CAPRI
unsigned int tries = 10000;
#endif
unsigned long timeout;
/* Reset host controller by setting 'Software Reset for All' */
sdhci_writeb(host, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
/* Wait for 100 ms max (100ms timeout is taken from sdhci.c) */
timeout = jiffies + msecs_to_jiffies(100);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
if (time_is_before_jiffies(timeout)) {
dev_err(dev->dev, "Error: sd host is in reset!!!\n");
return -EFAULT;
}
}
/* reset the host using the top level reset */
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
val |= KONA_SDHOST_RESET;
sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
do {
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
#ifdef CONFIG_ARCH_CAPRI
if (--tries <= 0)
break;
#endif
} while (0 == (val & KONA_SDHOST_RESET));
/* bring the host out of reset */
val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
val &= ~KONA_SDHOST_RESET;
/* Back-to-Back register write needs a delay of 1ms
* at bootup (min 10uS)
*/
udelay(1000);
sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
return 0;
}
示例14: sdhci_set_ios
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
u32 ctrl;
struct sdhci_host *host = mmc_priv(mmc);
if (host->ops.set_control_reg) {
host->ops.set_control_reg(host);
}
if (ios->clock != host->clock) {
sdhci_set_clock(mmc, ios->clock);
}
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (ios->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if ((host->sdhci_version & SDHCI_SPEC_VER_MASK) >=
SDHCI_SPEC_300) {
ctrl |= SDHCI_CTRL_8BITBUS;
}
} else {
if ((host->sdhci_version & SDHCI_SPEC_VER_MASK) >=
SDHCI_SPEC_300) {
ctrl &= ~SDHCI_CTRL_8BITBUS;
}
if (ios->bus_width == 4) {
ctrl |= SDHCI_CTRL_4BITBUS;
} else {
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
}
if (ios->clock > 26000000) {
ctrl |= SDHCI_CTRL_HISPD;
} else {
ctrl &= ~SDHCI_CTRL_HISPD;
}
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) {
ctrl &= ~SDHCI_CTRL_HISPD;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
示例15: sdhci_set_ios
static int sdhci_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int sdhci_set_ios(struct mmc *mmc)
{
#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
(host->quirks & SDHCI_QUIRK_USE_WIDE8))
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
(host->quirks & SDHCI_QUIRK_USE_WIDE8))
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
return 0;
}