C++ sc_create_vcd_trace_file函数代码示例

/// \brief Main function of the progam.
///
/// It's the most important function.
/// Generate the NoC system instantiating the NoC1 component.
/// Windows users: check the simulation time using 2 SYSTEMTIME variables and the function GetSystemTime from "windows.h".
/// For testing or to generate waves: use the technique shown in the code between //#INIT_WAVE and //#FINISH_WAVE. If not interested in waves, it is possible to cancel that part of code.
int sc_main (int argc,char *argv[])
{
		

	NoC_WR *NoC1;
	NoC1=new NoC_WR("NoC1");

	

	//SYSTEMTIME now,now1;
  
	//#INIT_WAVE
	sc_trace_file* tracefile;
	tracefile=sc_create_vcd_trace_file("wave");

	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkL,"clkL");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkR,"clkR");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datain,"L_datain");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datain,"R_datain");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_dataout,"L_dataout");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_dataout,"R_dataout");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_strobe_s,"L_strobe_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_strobe_s,"R_strobe_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datac_s,"L_datac_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datac_s,"R_datac_s");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_N,"save_register_N");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_P,"save_register_P");
	sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.saved_packet,"saved_packet");
	
	sc_trace_file* tracefile2;
	tracefile2=sc_create_vcd_trace_file("wave2");

	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkL,"clkL");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkR,"clkR");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datain,"L_datain");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datain,"R_datain");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_dataout,"L_dataout");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_dataout,"R_dataout");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_strobe_s,"L_strobe_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_strobe_s,"R_strobe_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datac_s,"L_datac_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datac_s,"R_datac_s");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[0],"datac_container[0]");
	sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[1],"datac_container[1]");
	//#FINISH_WAVE

	//GetSystemTime(&now);
		
	sc_start(1000,SC_NS);
	
	//GetSystemTime(&now1);
	//cout<<(now1.wMilliseconds-now.wMilliseconds)<<endl;

	//#INIT_WAVE
	sc_close_vcd_trace_file(tracefile);
	sc_close_vcd_trace_file(tracefile2);
	//#FINISH_WAVE
	
	return 0;
}

int sc_main(int, char **)
{
	sc_signal<bool> a, b, f;
	sc_clock clk("Clk", 20, SC_NS);	// 时钟周期为 20ns
	
	// 分别定义模块 NAND 和 TB 的实例，并通过局部变量（如 a、b）将这两个实例连接起来
	nand NAND("NAND");
	NAND.A(a);
	NAND.B(b);
	NAND.F(f);

	tb TB("TB");
	TB.clk(clk);
	TB.a(a);
	TB.b(b);
	TB.f(f);

	// 生成仿真结果波形文件
	sc_trace_file *tf = sc_create_vcd_trace_file("NAND");
	sc_trace(tf, NAND.A, "A");
	sc_trace(tf, NAND.B, "B");
	sc_trace(tf, NAND.F, "F");
	sc_trace(tf, TB.clk, "CLK");
	sc_start(200, SC_NS);	// 仿真时长 200ns
	sc_close_vcd_trace_file(tf);

	return 0;
}

int sc_main (int argc, char * argv[]) {
    sc_clock clk ("my_clock",1,0.5);
	ControlUnitTest *control = new ControlUnitTest("ControlUnitTest");
	control->clock(clk.signal());
	
	
	sc_trace_file *tf = sc_create_vcd_trace_file("ControlUnitTest");
	sc_trace(tf,control->clock,"clock");
	sc_trace(tf,control->iRInput,"iRInput");
	sc_trace(tf,control->statusBit,"statusBit");
	sc_trace(tf,control->ulaOp,"ulaOP");
	sc_trace(tf,control->ulaOutDemuxSel,"ulaOutDemuxSel");
	sc_trace(tf,control->ulaInAMuxSel,"ulaInAMuxSel");
	sc_trace(tf,control->ulaInBMuxSel,"ulaInBMuxSel");
	sc_trace(tf,control->rfSel,"rfSel");
	sc_trace(tf,control->rfReadWriteBit,"rfReadWriteBit");
	sc_trace(tf,control->writeMemory,"writeMemory");
	sc_trace(tf,control->loadRA,"loadRA");
	sc_trace(tf,control->loadRB,"loadRB");
	sc_trace(tf,control->loadIR,"loadIR");
	sc_trace(tf,control->loadAR,"loadAR");
	sc_trace(tf,control->loadPC,"loadPC");
	sc_trace(tf,control->loadDR,"loadDR");	
	
	
	sc_start();
	
	sc_close_vcd_trace_file(tf);
	return 0;
	
}

int sc_main(int argc, char* argv[]) {
	sc_signal<bool> input_1, input_2, output;
	sc_clock test_clock("TestClock", 10, SC_NS, 0.5);
	sc_trace_file *trace_file;
	
	stimulus stimulus_1("Stimulus");
	stimulus_1.input_1(input_1);
	stimulus_1.input_2(input_2);
	stimulus_1.clock(test_clock);
	
	monitor monitor_1("Monitor");
	monitor_1.input_1(input_1);
	monitor_1.input_2(input_2);
	monitor_1.output(output);
	monitor_1.clock(test_clock);

	xor_ xor_1("Xor");
	xor_1.input_1(input_1);
	xor_1.input_2(input_2);
	xor_1.output(output);

	trace_file = sc_create_vcd_trace_file("wave");


	sc_trace(trace_file, test_clock, "Clock");
	sc_trace(trace_file, input_1, "Input_1");
	sc_trace(trace_file, input_2, "Input_2");
	sc_trace(trace_file, output, "Output");

	sc_start();

	sc_close_vcd_trace_file(trace_file);

	return 0;
}

int sc_main(int argc, char* argv[])
{
	sc_signal <unsigned int> sinalA, sinalB, sinalC;
	sc_clock clock(" Clock", 10, SC_NS,0.5, 1, SC_NS);
	
	Estimulos est("Estimulos");
	Maior m("Maior");
	
	est.A(sinalA);
	est.B(sinalB);
	est.Clk(clock);
	
	m.A(sinalA);
	m.B(sinalB);
	m.C(sinalC);
	
	sc_trace_file* Tf;
	Tf = sc_create_vcd_trace_file("traces");
	sc_trace (Tf,sinalA,"A");
	sc_trace (Tf,sinalB,"B");
	sc_trace (Tf,sinalC,"C");
	sc_trace (Tf,clock,"Clk");
	
	sc_start();
	
	sc_close_vcd_trace_file(Tf);
	
	return 0;
}

/**
 * main
 */
int sc_main(int argc, char* argv[]) {

	sc_set_time_resolution(1, SC_PS);

	sc_clock clock("clk", 1, SC_NS);
	
	// Shift reg is declared but not implemented
	sc_signal<int> shiftreg_in;
	sc_signal<int> shiftreg_out;

	sc_trace_file *tf = sc_create_vcd_trace_file("wave");
	
	sc_write_comment(tf, "Simulation of Shift Reg at Elaboration Time Resolution");

	sc_trace(tf, clock, "Clock");
	sc_trace(tf, shiftreg_in, "shiftreg_in");
	sc_trace(tf, shiftreg_out, "shiftreg_out");

	sc_start(30, SC_NS);

	sc_close_vcd_trace_file(tf);

	system("pause");

	return 0;

}

int sc_main(int argc, char* argv[])
{
	// Turn off warnings due to deprecated features
	sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated",
		sc_core::SC_DO_NOTHING);

	// Declare the channel to communicate between or_gate and its TB
	sc_buffer<sc_logic> A, B, C;

	// MODULE INST USING POINTERS
	or_gate *OR;
	OR = new or_gate("OR");
	OR->a(A);// NAME BINDING
	OR->b(B);
	OR->c(C);

	TB_or_gate TB_OR("TB_OR"); 
	TB_OR.a(A); // NAME BINDING
	TB_OR.b(B);
	TB_OR.c(C);
	//TB_OR(A, B, C); // POSITIONAL BINDING

#ifdef WAVE
	// Generate waveform
	sc_trace_file *wf = sc_create_vcd_trace_file("OR_GATE");
	sc_trace(wf, OR->a, "a");
	sc_trace(wf, OR->b, "b");
	sc_trace(wf, OR->c, "c");
#endif
	sc_start(20, SC_NS);

	//sc_close_vcd_trace_file(wf);

	return(0);
}

int sc_main(int argc, char* argv[]) {

  sc_signal<int>  out_free ;
  sc_signal<int>  out_available ;
  sc_signal<bool> out_full ;
  sc_signal<bool> out_empty ;

  test_fifo u_test_fifo( "u_test_fifo" ) ;
  u_test_fifo.out_free     ( out_free );
  u_test_fifo.out_available( out_available );
  u_test_fifo.out_full     ( out_full );
  u_test_fifo.out_empty    ( out_empty );

  sc_trace_file * vcd_file;
  vcd_file = sc_create_vcd_trace_file( "test_fifo" );
  sc_trace( vcd_file , out_free      , "out_free" );
  sc_trace( vcd_file , out_available , "out_available" );
  sc_trace( vcd_file , out_full      , "out_full" );
  sc_trace( vcd_file , out_empty     , "out_empty" );

  sc_start(1000, SC_NS);

  sc_close_vcd_trace_file( vcd_file );

  return 0;
}

int sc_main(int argc, char* argv[]) {
  sc_signal<bool> t_a, t_b, t_cin, t_sum, t_cout;

  full_adder f1 ("FullAdderWithHalfAdder");
  // Positional association:
  f1 << t_a << t_b << t_cin << t_sum << t_cout;

  driver d1 ("GenerateWaveforms");
  d1 << t_a << t_b << t_cin;

  monitor mo1 ("MonitorWaveforms");
  mo1 << t_a << t_b << t_cin << t_sum << t_cout;

  if (! mo1.outfile) {
    cerr << "ERROR: Unable to open output file," << " fa_with_ha.out!\n";
    return (-2);
  }

  sc_trace_file *tf = sc_create_vcd_trace_file ("full_adder");
  sc_trace(tf, t_a,"A");
  sc_trace(tf, t_b, "B");
  sc_trace(tf, t_cin, "CarryIn");
  sc_trace(tf, t_sum, "Sum");
  sc_trace(tf, t_cout, "CarryOut");

  sc_start(100, SC_NS);

  // mo1.outfile.close();

  // d1.infile.close();
  sc_close_vcd_trace_file (tf);

  return(0);
}

int sc_main(int argc, char* argv[])
{
    sc_signal<bool> din, dout;

    sc_clock clk("clk",10,SC_NS,0.5,0, SC_NS,false);    // Create a clock signal
    
    delta DUT("delta");             // Instantiate Device Under Test

    DUT.din(din);                       // Connect ports
    DUT.dout(dout);
    DUT.clk(clk);

    sc_trace_file *fp;                  // Create VCD file
    fp=sc_create_vcd_trace_file("wave");// open(fp), create wave.vcd file
    fp->set_time_unit(100, SC_PS);      // set tracing resolution to ns
    sc_trace(fp,clk,"clk");             // Add signals to trace file
    sc_trace(fp,DUT.q_s,"q_s");
    sc_trace(fp,din,"din");

    sc_trace(fp,dout,"dout");

    sc_start(31, SC_NS);                // Run simulation
    din=true;                           
    sc_start(31, SC_NS);                // Run simulation
    din=false;                          
    sc_start(31, SC_NS);                // Run simulation

    sc_close_vcd_trace_file(fp);        // close(fp)

    return 0;
}

void anoc_init_simu() {

  // Resolution time ( time stamp ) in nano second;
#ifdef NC_SYSTEMC
  sc_set_time_resolution( 1, SC_NS );
#endif

  // transaction generation
#ifdef TLM_TRANS_RECORD  
  tlm_transrecord_database::enable_global_transaction_recording(); 
  if (tlm_transrecord_database::is_global_transaction_recording_enabled()) {
    tlm_transrecord_database::open_database(DATA_BASE_NAME, SC_NS);
  }
#endif // TLM_TRANS_RECORD

  // open & create trace file
#ifdef TRACE_VCD
  if (VCD_Record==true) {
    pt_trace_file = sc_create_vcd_trace_file(VCD_FILE_NAME);	// will automatically add .vcd extension
    ((vcd_trace_file *)pt_trace_file)->sc_set_vcd_time_unit(TIMESCALE);
  }
#endif // TRACE_VCD

  // Clean Stop SystemC
  signal(SIGINT,anoc_close_simu); // CTRL-C
}

int sc_main(int ac, char *av[])
{
  sc_trace_file *tf;
  sc_signal<bool> clock;
  sc_signal<int> I;
  sc_signal<char> C;
  sc_signal<float> F;
  sc_signal<sc_logic> L;

  proc1 P1("P1", clock, I, C, F, L);

  tf = sc_create_vcd_trace_file("test08");
  sc_trace(tf, clock, "Clock");
  sc_trace(tf, I, "Int", 32);
  sc_trace(tf, C, "Char", 8);
  sc_trace(tf, F, "Float");
  sc_trace(tf, L, "Logic");

  clock.write(0);
  sc_start(0, SC_NS);
  for (int i = 0; i< 10; i++) {
    clock.write(1);
    sc_start(10, SC_NS);
    clock.write(0);
    sc_start(10, SC_NS);
  }
  sc_close_vcd_trace_file( tf );
  return 0;
}

void test_miniuart()
{
	sc_set_time_resolution(1, SC_NS);

	sc_signal<bool> sys_clk, reset, int_rx, int_tx, txd_rxd;
	sc_signal_resolved ce, rd, wr;
	sc_signal_rv<2> addr;
	sc_signal_rv<8> data_in;
	sc_signal_rv<8> data_out;

	MiniUart MiniUart_inst("MiniUart");
		MiniUart_inst.sys_clk(sys_clk);
		MiniUart_inst.reset(reset);
		MiniUart_inst.ce(ce);
		MiniUart_inst.rd(rd);	
		MiniUart_inst.wr(wr);	
		MiniUart_inst.addr(addr);	
		MiniUart_inst.data_in(data_in);	
		MiniUart_inst.data_out(data_out);	

		MiniUart_inst.int_rx(int_rx);	
		MiniUart_inst.int_tx(int_tx);

		MiniUart_inst.rxd(txd_rxd);	
		MiniUart_inst.txd(txd_rxd);	

	RTL_TestBench RTL_TestBench_inst("RTL_TestBench");
		RTL_TestBench_inst.sys_clk(sys_clk);
		RTL_TestBench_inst.reset(reset);
		RTL_TestBench_inst.ce(ce);
		RTL_TestBench_inst.rd(rd);	
		RTL_TestBench_inst.wr(wr);	
		RTL_TestBench_inst.addr(addr);	
		RTL_TestBench_inst.data_in(data_out);	
		RTL_TestBench_inst.data_out(data_in);	

		RTL_TestBench_inst.int_rx(int_rx);	
		RTL_TestBench_inst.int_tx(int_tx);

	sc_trace_file *tf = sc_create_vcd_trace_file("wave_miniuart");
	sc_write_comment(tf, "Simulation of Mini Uart");
	((vcd_trace_file*)tf)->set_time_unit(1,SC_NS);	// 10exp(-9) = 1 ns

	sc_trace(tf,sys_clk, "sys_clk");
	sc_trace(tf,reset,"reset");
	sc_trace(tf,ce,"ce");
	sc_trace(tf,rd,"rd");
	sc_trace(tf,wr,"wr");
	sc_trace(tf,addr,"addr");
	sc_trace(tf,data_in,"data_in");
	sc_trace(tf,data_out,"data_out");
	sc_trace(tf,int_rx,"int_rx");
	sc_trace(tf,int_tx,"int_tx");
	sc_trace(tf,txd_rxd,"txd_rxd");

	sc_start(8, SC_MS);

	sc_close_vcd_trace_file(tf);
}

testbench::testbench(sc_module_name name) {

	p_inst = new processor("p_inst");
	t_inst = new transactor("t_inst", 25);
	tlm_bus_inst = new tlm_bus();
	m_inst = new MiniUart("m_inst");

	p_inst->p_slave(*tlm_bus_inst);
	t_inst->p_master(*tlm_bus_inst);

	t_inst->int_tx(int_tx);
	t_inst->int_rx(int_rx);
	t_inst->reset(reset);
	t_inst->ce(ce);
	t_inst->rd(rd);
	t_inst->wr(wr);
	t_inst->addr(addr);
	t_inst->data_in(data_in);
	t_inst->data_out(data_out);
	
	m_inst->sys_clk(t_inst->sys_clk);
	m_inst->int_tx(int_tx);
	m_inst->int_rx(int_rx);
	m_inst->reset(reset);
	m_inst->ce(ce);
	m_inst->rd(rd);
	m_inst->wr(wr);
	m_inst->addr(addr);
	m_inst->data_in(data_out);
	m_inst->data_out(data_in);
	m_inst->txd(txd_rxd);
	m_inst->rxd(txd_rxd);

	tf = sc_create_vcd_trace_file("trans_trace");
	sc_write_comment(tf, "Simulation of Transactor");
	tf->set_time_unit(1, SC_NS);

	t_inst->sys_clk.trace(tf);

	sc_trace(tf, reset, "reset");
	sc_trace(tf, int_rx, "int_rx");
	sc_trace(tf, int_tx, "int_tx");
	sc_trace(tf, txd_rxd, "txd_rxd");
	sc_trace(tf, ce, "ce");
	sc_trace(tf, rd, "rd");
	sc_trace(tf, wr, "wr");
	sc_trace(tf, addr, "addr");
	sc_trace(tf, data_in, "data_in");
	sc_trace(tf, data_out, "data_out");
	
	sc_trace(tf, t_inst->p_master->getAddress(), "addr");
	sc_trace(tf, t_inst->p_master->getData(), "data");
	sc_trace(tf, t_inst->p_master->is_read(), "rw");

}

int sc_main(int argc, char* argv[]){

  sc_signal<bool> reset;
  sc_signal<bool> ld;
  sc_signal<bool> lshift;
  sc_signal<bool> rshift;
  sc_signal<bool> leftin;
  sc_signal<bool> rightin;
  sc_signal<sc_bv<8> > in;
  sc_signal<sc_bv<8> > out;
   
  sc_clock clk ("clk", 2, SC_US);	// a clock with a period of 2 �-sec
   
  shiftreg sr("sr0");
  sr.clk(clk);
  sr.reset(reset);
  sr.ld(ld);
  sr.lshift(lshift);
  sr.rshift(rshift);
  sr.leftin(leftin);
  sr.rightin(rightin);
  sr.in(in);
  sr.out(out);
  stim st("stim0");
  st.reset(reset);
  st.ld(ld);
  st.lshift(lshift);
  st.rshift(rshift);
  st.leftin(leftin);
  st.rightin(rightin);
  st.in(out);
  st.out(in);
  sc_trace_file *tf;				// Signal tracing
  tf=sc_create_vcd_trace_file("shiftreg");	// create new trace file
  tf->set_time_unit(0.5,SC_US);	// set time resolution to 0.5 �-sec (let's do a bit oversampling ;-))
  
  sc_trace(tf,clk,"clk");
  sc_trace(tf,reset,"reset");
  sc_trace(tf,ld,"ld");
  sc_trace(tf,lshift,"lshift");
  sc_trace(tf,rshift,"rshift");
  sc_trace(tf,leftin,"leftin");
  sc_trace(tf,rightin,"rightin");
  sc_trace(tf,in,"in");
  sc_trace(tf,out,"out");

  sc_start(100,SC_US);	// run the simulation for 100 �-sec
  
  sc_close_vcd_trace_file(tf);	// close trace file

return 0;

};