本文整理汇总了C++中samsung_rev函数的典型用法代码示例。如果您正苦于以下问题:C++ samsung_rev函数的具体用法?C++ samsung_rev怎么用?C++ samsung_rev使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了samsung_rev函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: exynos5_pm_prepare
static void exynos5_pm_prepare(void)
{
unsigned int tmp;
if (exynos5_sleep_gpio_table_set)
exynos5_sleep_gpio_table_set();
if (samsung_rev() < EXYNOS5250_REV_1_0) {
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
tmp &= ~(1 << 4);
__raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
}
/* Set value of power down register for sleep mode */
exynos5_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
if (exynos4_is_c2c_use()) {
tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
}
s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc));
}
示例2: exynos5250_target_for_mif
static void exynos5250_target_for_mif(struct busfreq_data *data, int div_index)
{
unsigned int tmp;
/* Change Divider - CDREX */
tmp = data->cdrex_divtable[div_index];
__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX);
if (samsung_rev() < EXYNOS5250_REV_1_0) {
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
} while (tmp & 0x11111111);
} else {
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
} while (tmp & 0x11110011); \
}
if (samsung_rev() < EXYNOS5250_REV_1_0) {
tmp = data->cdrex2_divtable[div_index];
__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX2);
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX2);
} while (tmp & 0x1);
}
}
示例3: exynos4_c2c_request_pwr_mode
void exynos4_c2c_request_pwr_mode(enum c2c_pwr_mode mode)
{
if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))
exynos4_config_for_c2c[0].val = 0x3;
else
exynos4_config_for_c2c[0].val = 0x0;
switch (mode) {
/* If C2C mode is MAXIMAL LATENCY */
case MAX_LATENCY:
exynos4_config_for_c2c[1].val = 0x0;
if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))
exynos4_config_for_c2c[2].val = 0x1;
else
exynos4_config_for_c2c[2].val = 0x0;
#ifdef CONFIG_EXYNOS_C2C
exynos4_config_for_c2c[3].val = 0x0;
#endif
break;
/* If C2C mode is Minimal or Short LATENCY */
default:
exynos4_config_for_c2c[1].val = 0x3;
exynos4_config_for_c2c[2].val = 0x1;
#ifdef CONFIG_EXYNOS_C2C
exynos4_config_for_c2c[3].val = 0x1;
#endif
break;
}
}
示例4: exynos4_setup_mshci_cfg_ddr
void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, int ddr)
{
if (ddr) {
#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
__raw_writel(0x00, DIV_FSYS3);
#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
__raw_writel(0x01, DIV_FSYS3);
#else
if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
samsung_rev() >= EXYNOS4412_REV_1_0) {
__raw_writel(0x1, DIV_FSYS3);
} else
__raw_writel(0x05, DIV_FSYS3);
#endif
} else {
#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
__raw_writel(0x01, DIV_FSYS3);
#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
__raw_writel(0x03, DIV_FSYS3);
#else
if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
samsung_rev() >= EXYNOS4412_REV_1_0)
__raw_writel(0x3, DIV_FSYS3);
else
__raw_writel(0xb, DIV_FSYS3);
#endif
}
}
示例5: exynos5_cpu_suspend
void exynos5_cpu_suspend(void)
{
unsigned int tmp;
/* Disable wakeup by EXT_GIC */
tmp = __raw_readl(EXYNOS5_WAKEUP_MASK);
tmp |= EXYNOS5_DEFAULT_WAKEUP_MACK;
__raw_writel(tmp, EXYNOS5_WAKEUP_MASK);
/*
* GPS LPI mask.
*/
if (samsung_rev() < EXYNOS5250_REV_1_0)
__raw_writel(0x10000, EXYNOS5_GPS_LPI);
if (samsung_rev() >= EXYNOS5250_REV_1_0)
exynos4_reset_assert_ctrl(0);
#ifdef CONFIG_ARM_TRUSTZONE
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
#else
/* issue the standby signal into the pm unit. */
cpu_do_idle();
#endif
}
示例6: mali_pegasus_dvfs_table_update
static mali_bool mali_pegasus_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(samsung_rev() < EXYNOS4412_REV_2_0)
step_num = MALI_DVFS_STEPS-1;
if(soc_is_exynos4412()) {
/*check it's pega-prime or pega-Q*/
if(samsung_rev() < EXYNOS4412_REV_2_0) {
step_num = MALI_DVFS_STEPS-1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_4412_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
/* For Pega-Prime e-fuse, add 25mV from default ASV table*/
else if((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) {
for (i = 0; i < step_num; i++) {
MALI_PRINT(("Pega-Prime e-fuse(add 25mV):::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
/* pega-prime default ASV table */
else {
for (i = 0; i < step_num; i++) {
MALI_PRINT(("pega-prime default ASV table:::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
}
示例7: mfc_power_off
int mfc_power_off(void)
{
#ifdef CONFIG_PM_RUNTIME
if ((soc_is_exynos4212() && (samsung_rev() < EXYNOS4212_REV_1_0)) ||
(soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_1)))
return 0;
else
return pm_runtime_put_sync(pm->device);
#else
atomic_set(&pm->power, 0);
return 0;
#endif
}
示例8: fimc_clk_rate
int fimc_clk_rate(void)
{
if (samsung_rev() >= EXYNOS4412_REV_2_0)
return 180000000;
else
return 166750000;
}
示例9: exynos5_sys_powerdown_conf
void exynos5_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = entry_cnt;
unsigned int i;
exynos5_init_pmu();
for (; count > 0; count--)
__raw_writel(exynos5_pmu_config[count - 1].val[mode],
exynos5_pmu_config[count - 1].reg);
if (samsung_rev() < EXYNOS5250_REV_1_0) {
for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_config_gps); i++) {
__raw_writel(exynos52xx_pmu_config_gps[i].val[mode],
exynos52xx_pmu_config_gps[i].reg);
}
}
if ((mode != SYS_AFTR) && (exynos4_is_c2c_use())) {
pr_info("%s power mode enter with C2C Enabling\n"
, (mode == SYS_LPA) ? "LPA" : "SLEEP");
for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_c2c_config); i++) {
__raw_writel(exynos52xx_pmu_c2c_config[i].val[mode],
exynos52xx_pmu_c2c_config[i].reg);
}
}
}
示例10: exynos4_pmu_cp_init
int exynos4_pmu_cp_init(void)
{
u32 cp_ctrl;
int ret = 0;
unsigned int gpio;
pr_info("%s\n", __func__);
if (samsung_rev() == EXYNOS3470_REV_2_0) {
gpio = EXYNOS4_GPM2(3);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(1));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_pd_cfg(gpio, S5P_GPIO_PD_OUTPUT1);
s5p_gpio_set_data(gpio, 1);
s5p_gpio_set_pd_pull(gpio, S3C_GPIO_PULL_NONE);
}
cp_ctrl = __raw_readl(EXYNOS3470_CP_CTRL);
cp_ctrl |= MASK_CP_PWRDN_DONE;
__raw_writel(cp_ctrl, EXYNOS3470_CP_CTRL);
#ifdef DEBUG_SLEEP_WITHOUT_CP
/* test purpose */
exynos4_set_cp_power_onoff(CP_POWER_ON);
exynos4_cp_reset();
exynos4_clear_cp_reset_req();
exynos4_set_cp_power_onoff(CP_POWER_OFF);
exynos4_set_cp_power_onoff(CP_POWER_ON);
#endif
return ret;
}
示例11: mali_dvfs_bottom_lock_push
int mali_dvfs_bottom_lock_push(int lock_step)
{
int prev_status = _mali_osk_atomic_read(&bottomlock_status);
if (prev_status < 0) {
MALI_PRINT(("gpu bottom lock status is not valid for push\n"));
return -1;
}
// not a bad idea to limit locking to 4th step, so let's leave this -gm
if (samsung_rev() < EXYNOS4412_REV_2_0)
lock_step = min(lock_step, MALI_DVFS_STEPS - 2);
else
lock_step = min(lock_step, MALI_DVFS_STEPS - 1);
if (bottom_lock_step < lock_step) {
bottom_lock_step = lock_step;
if (get_mali_dvfs_status() < lock_step) {
mali_regulator_set_voltage(mali_dvfs[lock_step].vol,
mali_dvfs[lock_step].vol);
mali_clk_set_rate(mali_dvfs[lock_step].clock,
mali_dvfs[lock_step].freq);
set_mali_dvfs_current_step(lock_step);
}
}
return _mali_osk_atomic_inc_return(&bottomlock_status);
}
示例12: mali_dvfs_table_update
static mali_bool mali_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(soc_is_exynos4412()) {
if (exynos_armclk_max == 1000000) {
step_num = MALI_DVFS_STEPS - 1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1ghz_type\n", i, mali_dvfs[i].vol));
}
} else if (samsung_rev() >= EXYNOS4412_REV_2_0) {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1.6ghz_type\n", i, mali_dvfs[i].vol));
}
} else {
step_num = MALI_DVFS_STEPS - 1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1.4ghz_type\n", i, mali_dvfs[i].vol));
}
}
}
return MALI_TRUE;
}
示例13: scu_enable
/*
* Enable the SCU
*/
void scu_enable(void __iomem *scu_base)
{
u32 scu_ctrl;
#ifdef CONFIG_ARM_ERRATA_764369
/* Cortex-A9 only */
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
scu_ctrl = __raw_readl(scu_base + 0x30);
if (!(scu_ctrl & 1))
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
}
#endif
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
/* already enabled? */
if (scu_ctrl & 1)
return;
if ((soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) ||
soc_is_exynos4210())
scu_ctrl |= (1<<3);
scu_ctrl |= 1;
__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
/*
* Ensure that the data accessed by CPU0 before the SCU was
* initialised is visible to the other CPUs.
*/
flush_cache_all();
#ifdef CONFIG_MACH_PX
logbuf_force_unlock();
#endif
}
示例14: exynos5_odroidxu_mmc_init
void __init exynos5_odroidxu_mmc_init(void)
{
int OM_STAT=0;
if (samsung_rev() < EXYNOS5410_REV_1_0)
smdk5410_dwmci0_pdata.caps &=
~(MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR);
#ifndef CONFIG_EXYNOS_EMMC_HS200
smdk5410_dwmci0_pdata.caps2 &=
~MMC_CAP2_HS200_1_8V_SDR;
#endif
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
OM_STAT = readl(EXYNOS_OM_STAT);
if(OM_STAT == 0x4) { // T-Flash_CH2
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
platform_add_devices(odroidxu_tflash_devices, ARRAY_SIZE(odroidxu_tflash_devices));
}
else { // emmc44_CH0
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
platform_add_devices(odroidxu_emmc_devices, ARRAY_SIZE(odroidxu_emmc_devices));
}
}
示例15: exynos_dwmci2_get_bus_wd
static int exynos_dwmci2_get_bus_wd(u32 slot_id)
{
if (samsung_rev() < EXYNOS5410_REV_1_0)
return 1;
else
return 4;
}