C++ saa7146_write函数代码示例

int ttpci_budget_debiwrite(struct budget *budget, u32 config, int addr,
			   int count, u32 value, int uselocks, int nobusyloop)
{
	struct saa7146_dev *saa = budget->dev;
	unsigned long flags = 0;
	int result;

	if (count > 4 || count <= 0)
		return 0;

	if (uselocks)
		spin_lock_irqsave(&budget->debilock, flags);

	if ((result = saa7146_wait_for_debi_done(saa, nobusyloop)) < 0) {
		if (uselocks)
			spin_unlock_irqrestore(&budget->debilock, flags);
		return result;
	}

	saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x00000 | (addr & 0xffff));
	saa7146_write(saa, DEBI_CONFIG, config);
	saa7146_write(saa, DEBI_PAGE, 0);
	saa7146_write(saa, DEBI_AD, value);
	saa7146_write(saa, MC2, (2 << 16) | 2);

	if ((result = saa7146_wait_for_debi_done(saa, nobusyloop)) < 0) {
		if (uselocks)
			spin_unlock_irqrestore(&budget->debilock, flags);
		return result;
	}

	if (uselocks)
		spin_unlock_irqrestore(&budget->debilock, flags);
	return 0;
}

static int vbi_open(struct saa7146_dev *dev, struct file *file)
{
    struct saa7146_fh *fh = file->private_data;

    u32 arbtr_ctrl	= saa7146_read(dev, PCI_BT_V1);
    int ret = 0;

    DEB_VBI(("dev:%p, fh:%p\n",dev,fh));

    ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
    if (0 == ret) {
        DEB_S(("cannot get vbi RESOURCE_DMA3_BRS resource\n"));
        return -EBUSY;
    }

    /* adjust arbitrition control for video dma 3 */
    arbtr_ctrl &= ~0x1f0000;
    arbtr_ctrl |=  0x1d0000;
    saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
    saa7146_write(dev, MC2, (MASK_04|MASK_20));

    memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt));

    fh->vbi_fmt.sampling_rate	= 27000000;
    fh->vbi_fmt.offset		= 248; /* todo */
    fh->vbi_fmt.samples_per_line	= vbi_pixel_to_capture;
    fh->vbi_fmt.sample_format	= V4L2_PIX_FMT_GREY;

    fh->vbi_fmt.start[0] = 5;
    fh->vbi_fmt.count[0] = 16;
    fh->vbi_fmt.start[1] = 312;
    fh->vbi_fmt.count[1] = 16;

    videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
                           &dev->pci->dev, &dev->slock,
                           V4L2_BUF_TYPE_VBI_CAPTURE,
                           V4L2_FIELD_SEQ_TB,
                           sizeof(struct saa7146_buf),
                           file);

    init_timer(&fh->vbi_read_timeout);
    fh->vbi_read_timeout.function = vbi_read_timeout;
    fh->vbi_read_timeout.data = (unsigned long)file;

    /* initialize the brs */
    if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
        saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
    } else {
        saa7146_write(dev, BRS_CTRL, 0x00000001);

        if (0 != (ret = vbi_workaround(dev))) {
            DEB_VBI(("vbi workaround failed!\n"));
            /* return ret;*/
        }
    }

    /* upload brs register */
    saa7146_write(dev, MC2, (MASK_08|MASK_24));
    return 0;
}

static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *standard)
{
	struct mxb *mxb = (struct mxb *)dev->ext_priv;

	if (V4L2_STD_PAL_I == standard->id) {
		v4l2_std_id std = V4L2_STD_PAL_I;

		DEB_D(("VIDIOC_S_STD: setting mxb for PAL_I.\n"));
		/* set the 7146 gpio register -- I don't know what this does exactly */
		saa7146_write(dev, GPIO_CTRL, 0x00404050);
		/* unset the 7111 gpio register -- I don't know what this does exactly */
		saa7111a_call(mxb, core, s_gpio, 0);
		tuner_call(mxb, core, s_std, std);
	} else {
		v4l2_std_id std = V4L2_STD_PAL_BG;

		DEB_D(("VIDIOC_S_STD: setting mxb for PAL/NTSC/SECAM.\n"));
		/* set the 7146 gpio register -- I don't know what this does exactly */
		saa7146_write(dev, GPIO_CTRL, 0x00404050);
		/* set the 7111 gpio register -- I don't know what this does exactly */
		saa7111a_call(mxb, core, s_gpio, 1);
		tuner_call(mxb, core, s_std, std);
	}
	return 0;
}

static int std_callback(struct saa7146_dev *dev, struct saa7146_standard *standard)
{
    struct mxb *mxb = (struct mxb *)dev->ext_priv;

    if (V4L2_STD_PAL_I == standard->id) {
        v4l2_std_id std = V4L2_STD_PAL_I;

        DEB_D("VIDIOC_S_STD: setting mxb for PAL_I\n");

        saa7146_write(dev, GPIO_CTRL, 0x00404050);

        saa7111a_call(mxb, core, s_gpio, 0);
        tuner_call(mxb, core, s_std, std);
    } else {
        v4l2_std_id std = V4L2_STD_PAL_BG;

        DEB_D("VIDIOC_S_STD: setting mxb for PAL/NTSC/SECAM\n");

        saa7146_write(dev, GPIO_CTRL, 0x00404050);

        saa7111a_call(mxb, core, s_gpio, 1);
        tuner_call(mxb, core, s_std, std);
    }
    return 0;
}

static void vbi_stop(struct saa7146_fh *fh, struct file *file)
{
	struct saa7146_dev *dev = fh->dev;
	struct saa7146_vv *vv = dev->vv_data;
	unsigned long flags;
	DEB_VBI("dev:%p, fh:%p\n", dev, fh);

	spin_lock_irqsave(&dev->slock,flags);

	/* disable rps1  */
	saa7146_write(dev, MC1, MASK_29);

	/* disable rps1 irqs */
	SAA7146_IER_DISABLE(dev, MASK_28);

	/* shut down dma 3 transfers */
	saa7146_write(dev, MC1, MASK_20);

	if (vv->vbi_dmaq.curr)
		saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE);

	videobuf_queue_cancel(&fh->vbi_q);

	vv->vbi_streaming = NULL;

	del_timer(&vv->vbi_dmaq.timeout);
	del_timer(&vv->vbi_read_timeout);

	spin_unlock_irqrestore(&dev->slock, flags);
}

static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
{
	struct saa7146_vv *vv = dev->vv_data;

	struct saa7146_video_dma vdma3;

	int count = 0;
	unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
	unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;

	vdma3.base_even	= buf->pt[2].offset;
	vdma3.base_odd	= buf->pt[2].offset + 16 * vbi_pixel_to_capture;
	vdma3.prot_addr	= buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
	vdma3.pitch	= vbi_pixel_to_capture;
	vdma3.base_page	= buf->pt[2].dma | ME1;
	vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;

	saa7146_write_out_dma(dev, 3, &vdma3);

	/* write beginning of rps-program */
	count = 0;

	/* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */

	/* we don't wait here for the first field anymore. this is different from the video
	   capture and might cause that the first buffer is only half filled (with only
	   one field). but since this is some sort of streaming data, this is not that negative.
	   but by doing this, we can use the whole engine from videobuf-dma-sg.c... */

	/* set bit 1 */
	WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
	WRITE_RPS1(MASK_28 | MASK_12);

	/* turn on video-dma3 */
	WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
	WRITE_RPS1(MASK_04 | MASK_20);			/* => mask */
	WRITE_RPS1(MASK_04 | MASK_20);			/* => values */

	/* wait for o_fid_a/b / e_fid_a/b toggle */
	WRITE_RPS1(CMD_PAUSE | o_wait);
	WRITE_RPS1(CMD_PAUSE | e_wait);

	/* generate interrupt */
	WRITE_RPS1(CMD_INTERRUPT);

	/* stop */
	WRITE_RPS1(CMD_STOP);

	/* enable rps1 irqs */
	SAA7146_IER_ENABLE(dev, MASK_28);

	/* write the address of the rps-program */
	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);

	/* turn on rps */
	saa7146_write(dev, MC1, (MASK_13 | MASK_29));
}

static int video_end(struct saa7146_fh *fh, struct file *file)
{
	struct saa7146_dev *dev = fh->dev;
	struct saa7146_vv *vv = dev->vv_data;
	struct saa7146_format *fmt = NULL;
	unsigned long flags;
	unsigned int resource;
	u32 dmas = 0;
	DEB_EE(("dev:%p, fh:%p\n",dev,fh));

	if ((vv->video_status & STATUS_CAPTURE) != STATUS_CAPTURE) {
		DEB_S(("not capturing.\n"));
		return 0;
	}

	if (vv->video_fh != fh) {
		DEB_S(("capturing, but in another open.\n"));
		return -EBUSY;
	}

	fmt = format_by_fourcc(dev,fh->video_fmt.pixelformat);
	/* we need to have a valid format set here */
	BUG_ON(NULL == fmt);

	if (0 != (fmt->flags & FORMAT_IS_PLANAR)) {
		resource = RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP|RESOURCE_DMA3_BRS;
		dmas = MASK_22 | MASK_21 | MASK_20;
	} else {
		resource = RESOURCE_DMA1_HPS;
		dmas = MASK_22;
	}
	spin_lock_irqsave(&dev->slock,flags);

	/* disable rps0  */
	saa7146_write(dev, MC1, MASK_28);

	/* disable rps0 irqs */
	SAA7146_IER_DISABLE(dev, MASK_27);

	/* shut down all used video dma transfers */
	saa7146_write(dev, MC1, dmas);

	spin_unlock_irqrestore(&dev->slock, flags);

	vv->video_fh = NULL;
	vv->video_status = 0;

	saa7146_res_free(fh, resource);

	if (vv->ov_suspend != NULL) {
		saa7146_start_preview(vv->ov_suspend);
		vv->ov_suspend = NULL;
	}

	return 0;
}

static int vbi_open(struct saa7146_dev *dev, struct file *file)
{
	struct saa7146_fh *fh = file->private_data;
	struct saa7146_vv *vv = fh->dev->vv_data;

	u32 arbtr_ctrl	= saa7146_read(dev, PCI_BT_V1);
	int ret = 0;

	DEB_VBI("dev:%p, fh:%p\n", dev, fh);

	ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
	if (0 == ret) {
		DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
		return -EBUSY;
	}

	/* adjust arbitrition control for video dma 3 */
	arbtr_ctrl &= ~0x1f0000;
	arbtr_ctrl |=  0x1d0000;
	saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
	saa7146_write(dev, MC2, (MASK_04|MASK_20));

	videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
			    &dev->pci->dev, &dev->slock,
			    V4L2_BUF_TYPE_VBI_CAPTURE,
			    V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
			    sizeof(struct saa7146_buf),
			    file, &dev->v4l2_lock);

	vv->vbi_read_timeout.function = vbi_read_timeout;
	vv->vbi_read_timeout.data = (unsigned long)file;

	/* initialize the brs */
	if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
		saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
	} else {
		saa7146_write(dev, BRS_CTRL, 0x00000001);

		if (0 != (ret = vbi_workaround(dev))) {
			DEB_VBI("vbi workaround failed!\n");
			/* return ret;*/
		}
	}

	/* upload brs register */
	saa7146_write(dev, MC2, (MASK_08|MASK_24));
	return 0;
}

static int video_begin(struct saa7146_fh *fh)
{
	struct saa7146_dev *dev = fh->dev;
	struct saa7146_vv *vv = dev->vv_data;
	struct saa7146_format *fmt = NULL;
	unsigned int resource;
	int ret = 0, err = 0;

	DEB_EE(("dev:%p, fh:%p\n",dev,fh));

	if ((vv->video_status & STATUS_CAPTURE) != 0) {
		if (vv->video_fh == fh) {
			DEB_S(("already capturing.\n"));
			return 0;
		}
		DEB_S(("already capturing in another open.\n"));
		return -EBUSY;
	}

	if ((vv->video_status & STATUS_OVERLAY) != 0) {
		DEB_S(("warning: suspending overlay video for streaming capture.\n"));
		vv->ov_suspend = vv->video_fh;
		err = saa7146_stop_preview(vv->video_fh); /* side effect: video_status is now 0, video_fh is NULL */
		if (0 != err) {
			DEB_D(("suspending video failed. aborting\n"));
			return err;
		}
	}

	fmt = format_by_fourcc(dev,fh->video_fmt.pixelformat);
	/* we need to have a valid format set here */
	BUG_ON(NULL == fmt);

	if (0 != (fmt->flags & FORMAT_IS_PLANAR)) {
		resource = RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP|RESOURCE_DMA3_BRS;
	} else {
		resource = RESOURCE_DMA1_HPS;
	}

	ret = saa7146_res_get(fh, resource);
	if (0 == ret) {
		DEB_S(("cannot get capture resource %d\n",resource));
		if (vv->ov_suspend != NULL) {
			saa7146_start_preview(vv->ov_suspend);
			vv->ov_suspend = NULL;
		}
		return -EBUSY;
	}

	/* clear out beginning of streaming bit (rps register 0)*/
	saa7146_write(dev, MC2, MASK_27 );

	/* enable rps0 irqs */
	SAA7146_IER_ENABLE(dev, MASK_27);

	vv->video_fh = fh;
	vv->video_status = STATUS_CAPTURE;

	return 0;
}

/* interrupt handler */
static irqreturn_t interrupt_hw(int irq, void *dev_id)
{
	struct saa7146_dev *dev = dev_id;
	u32 isr;
	u32 ack_isr;

	/* read out the interrupt status register */
	ack_isr = isr = saa7146_read(dev, ISR);

	/* is this our interrupt? */
	if ( 0 == isr ) {
		/* nope, some other device */
		return IRQ_NONE;
	}

	if (dev->ext) {
		if (dev->ext->irq_mask & isr) {
			if (dev->ext->irq_func)
				dev->ext->irq_func(dev, &isr);
			isr &= ~dev->ext->irq_mask;
		}
	}
	if (0 != (isr & (MASK_27))) {
		DEB_INT(("irq: RPS0 (0x%08x).\n",isr));
		if (dev->vv_data && dev->vv_callback)
			dev->vv_callback(dev,isr);
		isr &= ~MASK_27;
	}
	if (0 != (isr & (MASK_28))) {
		if (dev->vv_data && dev->vv_callback)
			dev->vv_callback(dev,isr);
		isr &= ~MASK_28;
	}
	if (0 != (isr & (MASK_16|MASK_17))) {
		SAA7146_IER_DISABLE(dev, MASK_16|MASK_17);
		/* only wake up if we expect something */
		if (0 != dev->i2c_op) {
			dev->i2c_op = 0;
			wake_up(&dev->i2c_wq);
		} else {
			u32 psr = saa7146_read(dev, PSR);
			u32 ssr = saa7146_read(dev, SSR);
#ifdef CONFIG_DEBUG_PRINTK
			printk(KERN_WARNING "%s: unexpected i2c irq: isr %08x psr %08x ssr %08x\n",
			       dev->name, isr, psr, ssr);
#else
			;
#endif
		}
		isr &= ~(MASK_16|MASK_17);
	}
	if( 0 != isr ) {
		ERR(("warning: interrupt enabled, but not handled properly.(0x%08x)\n",isr));
		ERR(("disabling interrupt source(s)!\n"));
		SAA7146_IER_DISABLE(dev,isr);
	}
	saa7146_write(dev, ISR, ack_isr);
	return IRQ_HANDLED;
}

static int stop_ts_capture(struct budget *budget)
{
	dprintk(2, "budget: %p\n", budget);

	saa7146_write(budget->dev, MC1, MASK_20);	// DMA3 off
	SAA7146_IER_DISABLE(budget->dev, MASK_10);
	return 0;
}

static irqreturn_t interrupt_hw(int irq, void *dev_id)
{
	struct saa7146_dev *dev = dev_id;
	u32 isr;
	u32 ack_isr;

	
	ack_isr = isr = saa7146_read(dev, ISR);

	
	if ( 0 == isr ) {
		
		return IRQ_NONE;
	}

	if (dev->ext) {
		if (dev->ext->irq_mask & isr) {
			if (dev->ext->irq_func)
				dev->ext->irq_func(dev, &isr);
			isr &= ~dev->ext->irq_mask;
		}
	}
	if (0 != (isr & (MASK_27))) {
		DEB_INT("irq: RPS0 (0x%08x)\n", isr);
		if (dev->vv_data && dev->vv_callback)
			dev->vv_callback(dev,isr);
		isr &= ~MASK_27;
	}
	if (0 != (isr & (MASK_28))) {
		if (dev->vv_data && dev->vv_callback)
			dev->vv_callback(dev,isr);
		isr &= ~MASK_28;
	}
	if (0 != (isr & (MASK_16|MASK_17))) {
		SAA7146_IER_DISABLE(dev, MASK_16|MASK_17);
		
		if (0 != dev->i2c_op) {
			dev->i2c_op = 0;
			wake_up(&dev->i2c_wq);
		} else {
			u32 psr = saa7146_read(dev, PSR);
			u32 ssr = saa7146_read(dev, SSR);
			pr_warn("%s: unexpected i2c irq: isr %08x psr %08x ssr %08x\n",
				dev->name, isr, psr, ssr);
		}
		isr &= ~(MASK_16|MASK_17);
	}
	if( 0 != isr ) {
		ERR("warning: interrupt enabled, but not handled properly.(0x%08x)\n",
		    isr);
		ERR("disabling interrupt source(s)!\n");
		SAA7146_IER_DISABLE(dev,isr);
	}
	saa7146_write(dev, ISR, ack_isr);
	return IRQ_HANDLED;
}

static int ttpci_budget_debiwrite_nolock(struct budget *budget, u32 config,
		int addr, int count, u32 value, int nobusyloop)
{
	struct saa7146_dev *saa = budget->dev;
	int result;

	result = saa7146_wait_for_debi_done(saa, nobusyloop);
	if (result < 0)
		return result;

	saa7146_write(saa, DEBI_COMMAND, (count << 17) | 0x00000 | (addr & 0xffff));
	saa7146_write(saa, DEBI_CONFIG, config);
	saa7146_write(saa, DEBI_PAGE, 0);
	saa7146_write(saa, DEBI_AD, value);
	saa7146_write(saa, MC2, (2 << 16) | 2);

	result = saa7146_wait_for_debi_done(saa, nobusyloop);
	return result < 0 ? result : 0;
}

void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data)
{
    u32 value = 0;

    BUG_ON(port > 3);

    value = saa7146_read(dev, GPIO_CTRL);
    value &= ~(0xff << (8*port));
    value |= (data << (8*port));
    saa7146_write(dev, GPIO_CTRL, value);
}

static int stop_ts_capture(struct budget *budget)
{
	DEB_EE(("budget: %p\n",budget));

        if (--budget->feeding)
                return budget->feeding;

        saa7146_write(budget->dev, MC1, MASK_20); // DMA3 off
	IER_DISABLE(budget->dev, MASK_10);
        return 0;
}