C++ rt2x00pci_register_write函数代码示例

static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
{
	if (rt2x00_is_soc(rt2x00dev)) {
		rt2800_disable_radio(rt2x00dev);
		rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
		rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
	}
}

/*
 * Device state switch handlers.
 */
static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
				 enum dev_state state)
{
	int mask = (state == STATE_RADIO_IRQ_ON);
	u32 reg;
	unsigned long flags;

	/*
	 * When interrupts are being enabled, the interrupt registers
	 * should clear the register to assure a clean state.
	 */
	if (state == STATE_RADIO_IRQ_ON) {
		rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
		rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);

		/*
		 * Enable tasklets. The beacon related tasklets are
		 * enabled when the beacon queue is started.
		 */
		tasklet_enable(&rt2x00dev->txstatus_tasklet);
		tasklet_enable(&rt2x00dev->rxdone_tasklet);
		tasklet_enable(&rt2x00dev->autowake_tasklet);
	}

	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
	rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
	rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
	rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
	rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);

	if (state == STATE_RADIO_IRQ_OFF) {
		/*
		 * Ensure that all tasklets are finished before
		 * disabling the interrupts.
		 */
		tasklet_disable(&rt2x00dev->txstatus_tasklet);
		tasklet_disable(&rt2x00dev->rxdone_tasklet);
		tasklet_disable(&rt2x00dev->autowake_tasklet);
	}
}

static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
{
    struct rt2x00_dev *rt2x00dev = dev_instance;
    u32 reg, mask;

    /* Read status and ACK all interrupts */
    rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
    rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);

    if (!reg)
        return IRQ_NONE;

    if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
        return IRQ_HANDLED;

    /*
     * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
     * for interrupts and interrupt masks we can just use the value of
     * INT_SOURCE_CSR to create the interrupt mask.
     */
    mask = ~reg;

    if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
        rt2800pci_txstatus_interrupt(rt2x00dev);
        /*
         * Never disable the TX_FIFO_STATUS interrupt.
         */
        rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
    }

    if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
        tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);

    if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
        tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);

    if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
        tasklet_schedule(&rt2x00dev->rxdone_tasklet);

    if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
        tasklet_schedule(&rt2x00dev->autowake_tasklet);

    /*
     * Disable all interrupts for which a tasklet was scheduled right now,
     * the tasklet will reenable the appropriate interrupts.
     */
    spin_lock(&rt2x00dev->irqmask_lock);
    rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
    reg &= mask;
    rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
    spin_unlock(&rt2x00dev->irqmask_lock);

    return IRQ_HANDLED;
}

static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
				 struct rt2x00lib_erp *erp)
{
	int preamble_mask;
	u32 reg;

	/*
	 * When short preamble is enabled, we should set bit 0x08
	 */
	preamble_mask = erp->short_preamble << 3;

	rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
	rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
			   erp->ack_timeout);
	rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
			   erp->ack_consume_time);
	rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);

	rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
	rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
	rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
	rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);

	rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
	rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
	rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
	rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);

	rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
	rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
	rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
	rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);

	rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
	rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
	rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
	rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);

	rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);

	rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
	rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
	rt2x00pci_register_write(rt2x00dev, CSR11, reg);

	rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
	rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
	rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
	rt2x00pci_register_write(rt2x00dev, CSR18, reg);

	rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
	rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
	rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
	rt2x00pci_register_write(rt2x00dev, CSR19, reg);
}

static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
				    const enum data_queue_qid qid)
{
	u32 reg;

	if (qid == QID_BEACON) {
		rt2x00pci_register_write(rt2x00dev, CSR14, 0);
	} else {
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
	}
}

static void rt2400pci_kill_tx_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	if (queue->qid == QID_BEACON) {
		rt2x00pci_register_write(rt2x00dev, CSR14, 0);
	} else {
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
	}
}

static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
	if (state == STATE_AWAKE) {
		rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
		rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
	} else if (state == STATE_SLEEP) {
		rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
					 0xffffffff);
		rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
					 0xffffffff);
		rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
	}

	return 0;
}

/*
 * TX data initialization
 */
static void rt2400pci_write_beacon(struct queue_entry *entry)
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
	struct queue_entry_priv_pci *entry_priv = entry->priv_data;
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
	u32 word;
	u32 reg;

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
	rt2x00pci_register_write(rt2x00dev, CSR14, reg);

	/*
	 * Replace rt2x00lib allocated descriptor with the
	 * pointer to the _real_ hardware descriptor.
	 * After that, map the beacon to DMA and update the
	 * descriptor.
	 */
	memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
	skbdesc->desc = entry_priv->desc;

	rt2x00queue_map_txskb(rt2x00dev, entry->skb);

	rt2x00_desc_read(entry_priv->desc, 1, &word);
	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
	rt2x00_desc_write(entry_priv->desc, 1, word);
}

static void rt2800pci_clear_entry(struct queue_entry *entry)
{
    struct queue_entry_priv_pci *entry_priv = entry->priv_data;
    struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
    struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
    u32 word;

    if (entry->queue->qid == QID_RX) {
        rt2x00_desc_read(entry_priv->desc, 0, &word);
        rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
        rt2x00_desc_write(entry_priv->desc, 0, word);

        rt2x00_desc_read(entry_priv->desc, 1, &word);
        rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
        rt2x00_desc_write(entry_priv->desc, 1, word);

        /*
         * Set RX IDX in register to inform hardware that we have
         * handled this entry and it is available for reuse again.
         */
        rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
                                 entry->entry_idx);
    } else {
        rt2x00_desc_read(entry_priv->desc, 1, &word);
        rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
        rt2x00_desc_write(entry_priv->desc, 1, word);
    }
}

static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
				const unsigned int word, const u8 value)
{
	u32 reg;

	/*
	 * Wait until the BBP becomes ready.
	 */
	reg = rt2400pci_bbp_check(rt2x00dev);
	if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
		ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
		return;
	}

	/*
	 * Write the data into the BBP.
	 */
	reg = 0;
	rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
	rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
	rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
	rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);

	rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
}

static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
			       const unsigned int word, const u32 value)
{
	u32 reg;
	unsigned int i;

	if (!word)
		return;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
		if (!rt2x00_get_field32(reg, RFCSR_BUSY))
			goto rf_write;
		udelay(REGISTER_BUSY_DELAY);
	}

	ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
	return;

rf_write:
	reg = 0;
	rt2x00_set_field32(&reg, RFCSR_VALUE, value);
	rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
	rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
	rt2x00_set_field32(&reg, RFCSR_BUSY, 1);

	rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
	rt2x00_rf_write(rt2x00dev, word, value);
}

static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
{
	struct rt2x00_dev *rt2x00dev = dev_instance;
	u32 reg;

	/*
	 * Get the interrupt sources & saved to local variable.
	 * Write register value back to clear pending interrupts.
	 */
	rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
	rt2x00pci_register_write(rt2x00dev, CSR7, reg);

	if (!reg)
		return IRQ_NONE;

	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		return IRQ_HANDLED;

	/* Store irqvalues for use in the interrupt thread. */
	rt2x00dev->irqvalue[0] = reg;

	/* Disable interrupts, will be enabled again in the interrupt thread. */
	rt2x00dev->ops->lib->set_device_state(rt2x00dev,
					      STATE_RADIO_IRQ_OFF_ISR);

	return IRQ_WAKE_THREAD;
}

/*
 * Configuration handlers.
 */
static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
				    const unsigned int filter_flags)
{
	u32 reg;

	/*
	 * Start configuration steps.
	 * Note that the version error will always be dropped
	 * since there is no filter for it at this time.
	 */
	rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
			   !(filter_flags & FIF_FCSFAIL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
			   !(filter_flags & FIF_PLCPFAIL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
			   !(filter_flags & FIF_PROMISC_IN_BSS));
	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
			   !(filter_flags & FIF_PROMISC_IN_BSS) &&
			   !rt2x00dev->intf_ap_count);
	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
	rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}

static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
			       const unsigned int word, u8 *value)
{
	u32 reg;

	mutex_lock(&rt2x00dev->csr_mutex);

	/*
	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the read request into the register.
	 * After the data has been written, we wait until hardware
	 * returns the correct value, if at any time the register
	 * doesn't become available in time, reg will be 0xffffffff
	 * which means we return 0xff to the caller.
	 */
	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);

		rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);

		WAIT_FOR_BBP(rt2x00dev, &reg);
	}

	*value = rt2x00_get_field32(reg, BBPCSR_VALUE);

	mutex_unlock(&rt2x00dev->csr_mutex);
}

static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
	u32 reg;
	unsigned int i;
	char put_to_sleep;
	char bbp_state;
	char rf_state;

	put_to_sleep = (state != STATE_AWAKE);

	rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
	rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);

	/*
	 * Device is not guaranteed to be in the requested state yet.
	 * We must wait until the register indicates that the
	 * device has entered the correct state.
	 */
	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
		bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
		rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
		if (bbp_state == state && rf_state == state)
			return 0;
		msleep(10);
	}

	return -EBUSY;
}