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C++ res2mmio函数代码示例

本文整理汇总了C++中res2mmio函数的典型用法代码示例。如果您正苦于以下问题：C++ res2mmio函数的具体用法？C++ res2mmio怎么用？C++ res2mmio使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。


在下文中一共展示了res2mmio函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。

示例1: serialio_i2c_voltage_sel

/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
	u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
	reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
	reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
	write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:8，代码来源:serialio.c

示例2: gtt_read

static unsigned long gtt_read(unsigned long reg)
{
	u32 val;
	val = read32(res2mmio(gtt_res, reg, 0));
	return val;

}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:7，代码来源:igd.c

示例3: usb_ehci_init

static void usb_ehci_init(struct device *dev)
{
    struct resource *res;
    u8 *base;
    u32 reg32;
    u8 reg8;

    printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
    reg32 = pci_read_config32(dev, PCI_COMMAND);
    reg32 |= PCI_COMMAND_MASTER;
    reg32 |= PCI_COMMAND_SERR;
    pci_write_config32(dev, PCI_COMMAND, reg32);

    reg32 = pci_read_config32(dev, 0xdc);
    reg32 |= (1 << 31) | (1 << 27);
    pci_write_config32(dev, 0xdc, reg32);

    reg32 = pci_read_config32(dev, 0xfc);
    reg32 &= ~(3 << 2);
    reg32 |= (2 << 2) | (1 << 29) | (1 << 17);
    pci_write_config32(dev, 0xfc, reg32);

    /* Clear any pending port changes */
    res = find_resource(dev, 0x10);
    base = res2mmio(res, 0, 0);
    reg32 = read32(base + 0x24) | (1 << 2);
    write32(base + 0x24, reg32);

    /* workaround */
    reg8 = pci_read_config8(dev, 0x84);
    reg8 |= (1 << 4);
    pci_write_config8(dev, 0x84, reg8);

    printk(BIOS_DEBUG, "done.\n");
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:35，代码来源:usb_ehci.c

示例4: aza_init

static void aza_init(struct device *dev)
{
        u8 *base;
        struct resource *res;
        u32 codec_mask;

        printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");

//-------------- enable AZA (SiS7502) -------------------------
{
        u8  temp8;
        int i=0;
        while(SiS_SiS7502_init[i][0] != 0)
        {
                temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
                temp8 &= SiS_SiS7502_init[i][1];
                temp8 |= SiS_SiS7502_init[i][2];
                pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
                i++;
        };
}
//-----------------------------------------------------------


        // put audio to D0 state
        pci_write_config8(dev, 0x54,0x00);

#if DEBUG_AZA
{
        int i;

        printk(BIOS_DEBUG, "****** Azalia PCI config ******");
        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");

        for(i=0;i<0xff;i+=4){
                if((i%16)==0){
                        printk(BIOS_DEBUG, "\n%02x: ", i);
                }
                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
        }
        printk(BIOS_DEBUG, "\n");
}
#endif

	res = find_resource(dev, 0x10);
	if(!res)
		return;

	base = res2mmio(res, 0, 0);
	printk(BIOS_DEBUG, "base = 0x%p\n", base);

	codec_mask = codec_detect(base);

	if(codec_mask) {
		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
		codecs_init(base, codec_mask);
	}

        printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:60，代码来源:aza.c

示例5: azalia_init

static void azalia_init(struct device *dev)
{
	u8 *base;
	struct resource *res;
	u32 codec_mask;
	u32 reg32;

	/* Find base address */
	res = find_resource(dev, PCI_BASE_ADDRESS_0);
	if (!res)
		return;

	base = res2mmio(res, 0, 0);
	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);

	/* Set Bus Master */
	reg32 = pci_read_config32(dev, PCI_COMMAND);
	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);

	azalia_pch_init(dev, base);

	codec_mask = hda_codec_detect(base);

	if (codec_mask) {
		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
		codecs_init(base, codec_mask);
	}
}
开发者ID:tidatida，项目名称:coreboot，代码行数:28，代码来源:azalia.c

示例6: hda_init

static void hda_init(device_t dev)
{
	struct resource *res;
	int codec_mask;
	int i;
	u8 *base;

	reg_script_run_on_dev(dev, init_ops);

	res = find_resource(dev, PCI_BASE_ADDRESS_0);
	if (res == NULL)
		return;

	base = res2mmio(res, 0, 0);
	codec_mask = hda_codec_detect(base);

	printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
	if (!codec_mask)
		return;

	for (i = 3; i >= 0; i--) {
		if (!((1 << i) & codec_mask))
			continue;
		hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
				hdmi_codec_verb_table);
	}
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:27，代码来源:hda.c

示例7: serialio_d23_ltr

/* Enable LTR Auto Mode for D23:F0. */
static void serialio_d23_ltr(struct resource *bar0)
{
	u32 reg;

	/* Program BAR0 + 1008h[2] = 1b */
	reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
	reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);

	/* Program BAR0 + 1010h = 0x00000000 */
	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);

	/* Program BAR0 + 3Ch[30] = 1b */
	reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
	reg |= SIO_REG_SDIO_PPR_CMD12_B30;
	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
}
开发者ID:RafaelRMachado，项目名称:Coreboot，代码行数:18，代码来源:serialio.c

示例8: azalia_init

static void azalia_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
	u8 *base;
	u32 codec_mask, reg32;
	struct resource *res;
	u8 reg8;

	/* Set bus master. */
	reg32 = pci_read_config32(dev, PCI_COMMAND);
	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);

	pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused?

	reg8 = pci_read_config8(dev, 0x40);
	reg8 |= (1 << 3); /* Clear Clock Detect bit. */
	pci_write_config8(dev, 0x40, reg8);
	reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */
	pci_write_config8(dev, 0x40, reg8);
	reg8 |= (1 << 2); /* Enable clock detection. */
	pci_write_config8(dev, 0x40, reg8);
	mdelay(1);
	reg8 = pci_read_config8(dev, 0x40);
	printk(BIOS_DEBUG, "Azalia: codec type: %s\n",
	       (reg8 & (1 << 1)) ? "Azalia" : "AC97");

	reg8 = pci_read_config8(dev, 0x40); /* Audio control */
	reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */
	pci_write_config8(dev, 0x40, reg8);

	reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */
	reg8 &= ~(1 << 7); /* Docking not supported. */
	pci_write_config8(dev, 0x4d, reg8);

	res = find_resource(dev, 0x10);
	if (!res)
		return;

	/*
	 * NOTE: This will break as soon as the Azalia gets a BAR above
	 * 4G. Is there anything we can do about it?
	 */
	base = res2mmio(res, 0, 0);
	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
	codec_mask = codec_detect(base);

	if (codec_mask) {
		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
		codecs_init(dev, base, codec_mask);
	}
#endif
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:52，代码来源:azalia.c

示例9: hda_init

static void hda_init(struct device *dev)
{
	u8 byte;
	u32 dword;
	void *base;
	struct resource *res;
	u32 codec_mask;
	device_t sm_dev;

	/* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */
	byte = pm_ioread(0x59);
	byte |= 1 << 3;
	pm_iowrite(0x59, byte);

	/* Find the SMBus */
	/* FIXME: Need to find out why the call below crashes. */
	/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB700_SM, 0);*/
	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));

	/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
	pci_write_config32(sm_dev, 0xf8, 0x00);
	pci_write_config8(sm_dev, 0xfc, 0xAA);
	/* Set INTA - SMBus 0x63 [2..0] */
	byte = pci_read_config8(sm_dev, 0x63);
	byte &= ~0x7;
	byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
	pci_write_config8(sm_dev, 0x63, byte);

	/* Program the 2C to 0x437b1002 */
	dword = 0x437b1002;
	pci_write_config32(dev, 0x2c, dword);

	/* Read in BAR */
	/* Is this right? HDA allows for a 64-bit BAR
	 * but this is only setup for a 32-bit one
	 */
	res = find_resource(dev, 0x10);
	if (!res)
		return;

	base = res2mmio(res, 0, 0);
	printk(BIOS_DEBUG, "base = 0x%p\n", base);
	codec_mask = codec_detect(base);

	if (codec_mask) {
		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
		codecs_init(base, codec_mask);
	}
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:49，代码来源:hda.c

示例10: gma_func0_init

static void gma_func0_init(struct device *dev)
{
	u32 reg32;

	/* IGD needs to be Bus Master */
	reg32 = pci_read_config32(dev, PCI_COMMAND);
	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
	pci_write_config32(dev, PCI_COMMAND, reg32);

	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
		/* PCI Init, will run VBIOS */
		pci_dev_init(dev);
	} else {
		u32 physbase;
		struct resource *pio_res;
		struct northbridge_intel_pineview_config *conf = dev->chip_info;

		/* Find base addresses */
		mmio_res = find_resource(dev, 0x10);
		gtt_res = find_resource(dev, 0x1c);
		pio_res = find_resource(dev, 0x14);
		physbase = pci_read_config32(dev, 0x5c) & ~0xf;

		if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
			printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
			       mmio_res->base);
			intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0),
				res2mmio(gtt_res, 0, 0),
				physbase, pio_res->base);
		}

		/* Linux relies on VBT for panel info.  */
		generate_fake_intel_oprom(&conf->gfx, dev,
			"$VBT PINEVIEW       ");
	}
}
开发者ID:AdriDlu，项目名称:coreboot，代码行数:36，代码来源:gma.c

示例11: lpc_common_init

static void lpc_common_init(device_t dev)
{
	u32 dword;
	struct resource *res;

	/* I/O APIC initialization. */
	res = find_resource(dev, PCI_BASE_ADDRESS_1);  /* IOAPIC */
	ASSERT(res != NULL);
	setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */

#if 1
	dword = pci_read_config32(dev, 0xe4);
	dword |= (1 << 23);
	pci_write_config32(dev, 0xe4, dword);
#endif
}
开发者ID:tidatida，项目名称:coreboot，代码行数:16，代码来源:lpc.c

示例12: oxford_oxpcie_enable

static void oxford_oxpcie_enable(device_t dev)
{
	printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");

	struct resource *res = find_resource(dev, 0x10);
	if (!res) {
		printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
		return;
	}
	void *bar0 = res2mmio(res, 0, 0);

	printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
			(read32(bar0) >> 8), (read32(bar0) & 0xff));
	printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
			(read32(bar0 + 4) & 3));
	printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
}
开发者ID:tidatida，项目名称:coreboot，代码行数:17，代码来源:oxpcie.c

示例13: gma_func0_init

static void gma_func0_init(struct device *dev)
{
	u32 reg32;

	/* IGD needs to be Bus Master */
	reg32 = pci_read_config32(dev, PCI_COMMAND);
	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
	pci_write_config32(dev, PCI_COMMAND, reg32);

	/* Init graphics power management */
	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);

	struct northbridge_intel_gm45_config *conf = dev->chip_info;

	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
		/* PCI Init, will run VBIOS */
		pci_dev_init(dev);
	}

	/* Post VBIOS init */
	gma_pm_init_post_vbios(dev);

	if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
		u32 physbase;
		struct resource *lfb_res;
		struct resource *pio_res;

		lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
		pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);

		physbase = pci_read_config32(dev, 0x5c) & ~0xf;

		if (gtt_res && gtt_res->base && physbase && pio_res
		    && pio_res->base && lfb_res && lfb_res->base) {
			printk(BIOS_SPEW,
			       "Initializing VGA without OPROM. MMIO 0x%llx\n",
			       gtt_res->base);
			intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
				       pio_res->base, lfb_res->base);
		}

		/* Linux relies on VBT for panel info.  */
		generate_fake_intel_oprom(&conf->gfx, dev,
					  "$VBT IRONLAKE-MOBILE");
	}
}
开发者ID:MikeeHawk，项目名称:coreboot，代码行数:46，代码来源:gma.c

示例14: sata_init

static void sata_init(struct device *dev)
{
	uint8_t byte;

	u8 *mmio;
        struct resource *res;
        u8 *mmio_base;
	int i;

	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
		byte = pci_read_config8(dev, 0x78);
		byte |= (1<<7);
        	pci_write_config8(dev, 0x78, byte);

	        res = find_resource(dev, 0x24);
                mmio_base = res2mmio(res, 0, 3);

		write32(mmio_base + 0x10f0, 0x40000001);
		write32(mmio_base + 0x8c, 0x00ff2007);
                mdelay( 10 );
		write32(mmio_base + 0x8c, 0x78592009);
                mdelay( 10 );
		write32(mmio_base + 0x8c, 0x00082004);
                mdelay( 10 );
		write32(mmio_base + 0x8c, 0x00002004);
                mdelay( 10 );

		//init PHY

		printk(BIOS_DEBUG, "init PHY...\n");
		for(i=0; i<4; i++) {
			mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
			byte = read8(mmio + 0x40);
			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
			if(byte & 0x4) {// bit 2 is set
				byte = read8(mmio+0x48);
				write8(mmio + 0x48, byte | 1);
				write8(mmio + 0x48, byte & (~1));
	                        byte = read8(mmio + 0x40);
	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
			}
		}
	}
}
开发者ID:tidatida，项目名称:coreboot，代码行数:44，代码来源:sata.c

示例15: usb2_init

static void usb2_init(struct device *dev)
{
	u8 *base;
	struct resource *res;
	int i;
	u8  temp8;

	printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");

	//-------------- enable USB2.0 (SiS7002) ----------------------

	i = 0;
	while (SiS_SiS7002_init[i][0] != 0) {
		temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
		temp8 &= SiS_SiS7002_init[i][1];
		temp8 |= SiS_SiS7002_init[i][2];
		pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
		i++;
	};

	res = find_resource(dev, 0x10);
	if (!res)
		return;

	base = res2mmio(res, 0, 0);
	printk(BIOS_DEBUG, "base = 0x%p\n", base);
	write32(base + 0x20, 0x2);
	//-------------------------------------------------------------

#if DEBUG_USB2
	printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");

	for (i=0;i<0xff;i+=4) {
		if ((i%16)==0)
			printk(BIOS_DEBUG, "\n%02x: ", i);
		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
	}
	printk(BIOS_DEBUG, "\n");
#endif
	printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
}
开发者ID:lynxis，项目名称:coreboot-signed，代码行数:42，代码来源:usb2.c


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