本文整理汇总了C++中regmap_update_bits函数的典型用法代码示例。如果您正苦于以下问题:C++ regmap_update_bits函数的具体用法?C++ regmap_update_bits怎么用?C++ regmap_update_bits使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了regmap_update_bits函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: device_gpadc_init
static int __devinit device_gpadc_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
struct pm80x_subchip *subchip = chip->subchip;
struct regmap *map = subchip->regmap_gpadc;
int data = 0, mask = 0, ret = 0;
if (!map) {
dev_warn(chip->dev,
"Warning: gpadc regmap is not available!\n");
return -EINVAL;
}
/*
* initialize GPADC without activating it turn on GPADC
* measurments
*/
ret = regmap_update_bits(map,
PM800_GPADC_MISC_CONFIG2,
PM800_GPADC_MISC_GPFSM_EN,
PM800_GPADC_MISC_GPFSM_EN);
if (ret < 0)
goto out;
/*
* This function configures the ADC as requires for
* CP implementation.CP does not "own" the ADC configuration
* registers and relies on AP.
* Reason: enable automatic ADC measurements needed
* for CP to get VBAT and RF temperature readings.
*/
ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
if (ret < 0)
goto out;
ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
(PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
(PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
if (ret < 0)
goto out;
/*
* the defult of PM800 is GPADC operates at 100Ks/s rate
* and Number of GPADC slots with active current bias prior
* to GPADC sampling = 1 slot for all GPADCs set for
* Temprature mesurmants
*/
mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
if (pdata && (pdata->batt_det == 0))
data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
else
data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
PM800_GPADC_GP_BIAS_EN3);
ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
if (ret < 0)
goto out;
dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
return 0;
out:
dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
return ret;
}
示例2: max8973_init_dcdc
static int max8973_init_dcdc(struct max8973_chip *max,
struct max8973_regulator_platform_data *pdata)
{
int ret;
uint8_t control1 = 0;
uint8_t control2 = 0;
if (pdata->control_flags & MAX8973_CONTROL_REMOTE_SENSE_ENABLE)
control1 |= MAX8973_SNS_ENABLE;
if (!(pdata->control_flags & MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE))
control1 |= MAX8973_NFSR_ENABLE;
if (pdata->control_flags & MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE)
control1 |= MAX8973_AD_ENABLE;
if (pdata->control_flags & MAX8973_CONTROL_BIAS_ENABLE)
control1 |= MAX8973_BIAS_ENABLE;
if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
control1 |= MAX8973_FREQSHIFT_9PER;
/* Set ramp delay */
if (pdata->reg_init_data &&
pdata->reg_init_data->constraints.ramp_delay) {
if (pdata->reg_init_data->constraints.ramp_delay < 25000)
control1 |= MAX8973_RAMP_12mV_PER_US;
else if (pdata->reg_init_data->constraints.ramp_delay < 50000)
control1 |= MAX8973_RAMP_25mV_PER_US;
else if (pdata->reg_init_data->constraints.ramp_delay < 200000)
control1 |= MAX8973_RAMP_50mV_PER_US;
else
control1 |= MAX8973_RAMP_200mV_PER_US;
} else {
control1 |= MAX8973_RAMP_12mV_PER_US;
max->desc.ramp_delay = 12500;
}
if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
control2 |= MAX8973_DISCH_ENBABLE;
/* Clock advance trip configuration */
switch (pdata->control_flags & MAX8973_CONTROL_CLKADV_TRIP_MASK) {
case MAX8973_CONTROL_CLKADV_TRIP_DISABLED:
control2 |= MAX8973_CKKADV_TRIP_DISABLE;
break;
case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US:
control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US;
break;
case MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US:
control2 |= MAX8973_CKKADV_TRIP_150mV_PER_US;
break;
case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US_HIST_DIS:
control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US_HIST_DIS;
break;
}
/* Configure inductor value */
switch (pdata->control_flags & MAX8973_CONTROL_INDUCTOR_VALUE_MASK) {
case MAX8973_CONTROL_INDUCTOR_VALUE_NOMINAL:
control2 |= MAX8973_INDUCTOR_NOMINAL;
break;
case MAX8973_CONTROL_INDUCTOR_VALUE_MINUS_30_PER:
control2 |= MAX8973_INDUCTOR_MIN_30_PER;
break;
case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_30_PER:
control2 |= MAX8973_INDUCTOR_PLUS_30_PER;
break;
case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_60_PER:
control2 |= MAX8973_INDUCTOR_PLUS_60_PER;
break;
}
ret = regmap_write(max->regmap, MAX8973_CONTROL1, control1);
if (ret < 0) {
dev_err(max->dev, "register %d write failed, err = %d",
MAX8973_CONTROL1, ret);
return ret;
}
ret = regmap_write(max->regmap, MAX8973_CONTROL2, control2);
if (ret < 0) {
dev_err(max->dev, "register %d write failed, err = %d",
MAX8973_CONTROL2, ret);
return ret;
}
/* If external control is enabled then disable EN bit */
if (max->enable_external_control) {
ret = regmap_update_bits(max->regmap, MAX8973_VOUT,
MAX8973_VOUT_ENABLE, 0);
if (ret < 0)
dev_err(max->dev, "register %d update failed, err = %d",
MAX8973_VOUT, ret);
//.........这里部分代码省略.........
示例3: uda134x_hw_params
static int uda134x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
unsigned int hw_params = 0;
if (substream == uda134x->slave_substream) {
pr_debug("%s ignoring hw_params for slave substream\n",
__func__);
return 0;
}
pr_debug("%s sysclk: %d, rate:%d\n", __func__,
uda134x->sysclk, params_rate(params));
/* set SYSCLK / fs ratio */
switch (uda134x->sysclk / params_rate(params)) {
case 512:
break;
case 384:
hw_params |= (1<<4);
break;
case 256:
hw_params |= (1<<5);
break;
default:
printk(KERN_ERR "%s unsupported fs\n", __func__);
return -EINVAL;
}
pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
uda134x->dai_fmt, params_format(params));
/* set DAI format and word length */
switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 16:
hw_params |= (1<<1);
break;
case 18:
hw_params |= (1<<2);
break;
case 20:
hw_params |= ((1<<2) | (1<<1));
break;
default:
printk(KERN_ERR "%s unsupported format (right)\n",
__func__);
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_LEFT_J:
hw_params |= (1<<3);
break;
default:
printk(KERN_ERR "%s unsupported format\n", __func__);
return -EINVAL;
}
return regmap_update_bits(uda134x->regmap, UDA134X_STATUS0,
STATUS0_SYSCLK_MASK | STATUS0_DAIFMT_MASK, hw_params);
}
示例4: sec_reg_update
int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask)
{
return regmap_update_bits(sec_pmic->regmap, reg, mask, val);
}
示例5: bcm2835_i2s_clear_fifos
static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
bool tx, bool rx)
{
int timeout = 1000;
uint32_t syncval;
uint32_t csreg;
uint32_t i2s_active_state;
bool clk_was_prepared;
uint32_t off;
uint32_t clr;
off = tx ? BCM2835_I2S_TXON : 0;
off |= rx ? BCM2835_I2S_RXON : 0;
clr = tx ? BCM2835_I2S_TXCLR : 0;
clr |= rx ? BCM2835_I2S_RXCLR : 0;
/* Backup the current state */
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
/* Start clock if not running */
clk_was_prepared = dev->clk_prepared;
if (!clk_was_prepared)
bcm2835_i2s_start_clock(dev);
/* Stop I2S module */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
/*
* Clear the FIFOs
* Requires at least 2 PCM clock cycles to take effect
*/
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
/* Wait for 2 PCM clock cycles */
/*
* Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
* FIXME: This does not seem to work for slave mode!
*/
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
syncval &= BCM2835_I2S_SYNC;
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_SYNC, ~syncval);
/* Wait for the SYNC flag changing it's state */
while (--timeout) {
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
if ((csreg & BCM2835_I2S_SYNC) != syncval)
break;
}
if (!timeout)
dev_err(dev->dev, "I2S SYNC error!\n");
/* Stop clock if it was not running before */
if (!clk_was_prepared)
bcm2835_i2s_stop_clock(dev);
/* Restore I2S state */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
}
示例6: fsl_esai_set_dai_fmt
static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
u32 xcr = 0, xccr = 0, mask;
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Data on rising edge of bclk, frame low, 1clk before data */
xcr |= ESAI_xCR_xFSR;
xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_LEFT_J:
/* Data on rising edge of bclk, frame high */
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_RIGHT_J:
/* Data on rising edge of bclk, frame high, right aligned */
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
break;
case SND_SOC_DAIFMT_DSP_A:
/* Data on rising edge of bclk, frame high, 1clk before data */
xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_DSP_B:
/* Data on rising edge of bclk, frame high */
xcr |= ESAI_xCR_xFSL;
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
default:
return -EINVAL;
}
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/* Nothing to do for both normal cases */
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
xccr ^= ESAI_xCCR_xFSP;
break;
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
break;
default:
return -EINVAL;
}
esai_priv->slave_mode = false;
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
esai_priv->slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFM:
xccr |= ESAI_xCCR_xCKD;
break;
case SND_SOC_DAIFMT_CBM_CFS:
xccr |= ESAI_xCCR_xFSD;
break;
case SND_SOC_DAIFMT_CBS_CFS:
xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
break;
default:
return -EINVAL;
}
mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
return 0;
}
示例7: arizona_set_fll
int arizona_set_fll(struct arizona_fll *fll, int source,
unsigned int Fref, unsigned int Fout)
{
struct arizona *arizona = fll->arizona;
struct arizona_fll_cfg cfg, sync;
unsigned int reg, val;
int syncsrc;
bool ena;
int ret;
ret = regmap_read(arizona->regmap, fll->base + 1, ®);
if (ret != 0) {
arizona_fll_err(fll, "Failed to read current state: %d\n",
ret);
return ret;
}
ena = reg & ARIZONA_FLL1_ENA;
if (Fout) {
/* Do we have a 32kHz reference? */
regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
switch (val & ARIZONA_CLK_32K_SRC_MASK) {
case ARIZONA_CLK_SRC_MCLK1:
case ARIZONA_CLK_SRC_MCLK2:
syncsrc = val & ARIZONA_CLK_32K_SRC_MASK;
break;
default:
syncsrc = -1;
}
if (source == syncsrc)
syncsrc = -1;
if (syncsrc >= 0) {
ret = arizona_calc_fll(fll, &sync, Fref, Fout);
if (ret != 0)
return ret;
ret = arizona_calc_fll(fll, &cfg, 32768, Fout);
if (ret != 0)
return ret;
} else {
ret = arizona_calc_fll(fll, &cfg, Fref, Fout);
if (ret != 0)
return ret;
}
} else {
regmap_update_bits(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_ENA, 0);
regmap_update_bits(arizona->regmap, fll->base + 0x11,
ARIZONA_FLL1_SYNC_ENA, 0);
if (ena)
pm_runtime_put_autosuspend(arizona->dev);
return 0;
}
regmap_update_bits(arizona->regmap, fll->base + 5,
ARIZONA_FLL1_OUTDIV_MASK,
cfg.outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
if (syncsrc >= 0) {
arizona_apply_fll(arizona, fll->base, &cfg, syncsrc);
arizona_apply_fll(arizona, fll->base + 0x10, &sync, source);
} else {
arizona_apply_fll(arizona, fll->base, &cfg, source);
}
if (!ena)
pm_runtime_get(arizona->dev);
/* Clear any pending completions */
try_wait_for_completion(&fll->ok);
regmap_update_bits(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
if (syncsrc >= 0)
regmap_update_bits(arizona->regmap, fll->base + 0x11,
ARIZONA_FLL1_SYNC_ENA,
ARIZONA_FLL1_SYNC_ENA);
ret = wait_for_completion_timeout(&fll->ok,
msecs_to_jiffies(25));
if (ret == 0)
arizona_fll_warn(fll, "Timed out waiting for lock\n");
return 0;
}
示例8: pm8xxx_read_channel_rsv
static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
const struct pm8xxx_chan_info *ch,
u8 rsv, u16 *adc_code,
bool force_ratiometric)
{
int ret;
unsigned int val;
u8 rsvmask, rsvval;
u8 lsb, msb;
dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
ch->name, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
mutex_lock(&adc->lock);
/* Mux in this channel */
val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
if (ret)
goto unlock;
/* Set up ratiometric scale value, mask off all bits except these */
rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
if (adc->variant->broken_ratiometric && !force_ratiometric) {
/*
* Apparently the PM8058 has some kind of bug which is
* reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
* which just hardcodes the RSV selector to SEL1 (0x20) for
* most cases and SEL0 (0x10) for the MUXOFF channel only.
* If we force ratiometric (currently only done when attempting
* to do ratiometric calibration) this doesn't seem to work
* very well and I suspect ratiometric conversion is simply
* broken or not supported on the PM8058.
*
* Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
* the mode alone.
*
* Some PM8058 register documentation would be nice to get
* this right.
*/
if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
else
rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
} else {
if (rsv == 0xff)
rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
ADC_ARB_USRP_RSV_TRM;
else
rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
ADC_ARB_USRP_RSV_TRM;
}
ret = regmap_update_bits(adc->map,
ADC_ARB_USRP_RSV,
~rsvmask,
rsvval);
if (ret)
goto unlock;
ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
ADC_ARB_USRP_ANA_PARAM_DIS);
if (ret)
goto unlock;
/* Decimation factor */
ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
if (ret)
goto unlock;
ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
ADC_ARB_USRP_ANA_PARAM_EN);
if (ret)
goto unlock;
/* Enable the arbiter, the Qualcomm code does it twice like this */
ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
ADC_ARB_USRP_CNTRL_EN_ARB);
if (ret)
goto unlock;
ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
ADC_ARB_USRP_CNTRL_EN_ARB);
if (ret)
goto unlock;
/* Fire a request! */
reinit_completion(&adc->complete);
ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
ADC_ARB_USRP_CNTRL_EN_ARB |
ADC_ARB_USRP_CNTRL_REQ);
if (ret)
goto unlock;
/* Next the interrupt occurs */
//.........这里部分代码省略.........
示例9: exynos4x12_phy_pwr
static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
{
struct samsung_usb2_phy_driver *drv = inst->drv;
u32 rstbits = 0;
u32 phypwr = 0;
u32 rst;
u32 pwr;
u32 mode = 0;
u32 switch_mode = 0;
switch (inst->cfg->id) {
case EXYNOS4x12_DEVICE:
phypwr = EXYNOS_4x12_UPHYPWR_PHY0;
rstbits = EXYNOS_4x12_URSTCON_PHY0;
mode = EXYNOS_4x12_MODE_SWITCH_DEVICE;
switch_mode = 1;
break;
case EXYNOS4x12_HOST:
phypwr = EXYNOS_4x12_UPHYPWR_PHY1;
rstbits = EXYNOS_4x12_URSTCON_HOST_PHY;
mode = EXYNOS_4x12_MODE_SWITCH_HOST;
switch_mode = 1;
break;
case EXYNOS4x12_HSIC0:
phypwr = EXYNOS_4x12_UPHYPWR_HSIC0;
rstbits = EXYNOS_4x12_URSTCON_HSIC1 |
EXYNOS_4x12_URSTCON_HOST_LINK_P0 |
EXYNOS_4x12_URSTCON_HOST_PHY;
break;
case EXYNOS4x12_HSIC1:
phypwr = EXYNOS_4x12_UPHYPWR_HSIC1;
rstbits = EXYNOS_4x12_URSTCON_HSIC1 |
EXYNOS_4x12_URSTCON_HOST_LINK_P1;
break;
};
if (on) {
if (switch_mode)
regmap_update_bits(drv->reg_sys,
EXYNOS_4x12_MODE_SWITCH_OFFSET,
EXYNOS_4x12_MODE_SWITCH_MASK, mode);
pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
pwr &= ~phypwr;
writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST);
rst |= rstbits;
writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
udelay(10);
rst &= ~rstbits;
writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
/* The following delay is necessary for the reset sequence to be
* completed */
udelay(80);
} else {
pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
pwr |= phypwr;
writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
}
}
示例10: rk808_rtc_probe
static int rk808_rtc_probe(struct platform_device *pdev)
{
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
struct rk808_rtc *rk808_rtc;
struct rtc_time tm;
int ret;
rk808_rtc = devm_kzalloc(&pdev->dev, sizeof(*rk808_rtc), GFP_KERNEL);
if (rk808_rtc == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, rk808_rtc);
rk808_rtc->rk808 = rk808;
/* start rtc running by default, and use shadowed timer. */
ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG,
BIT_RTC_CTRL_REG_STOP_RTC_M |
BIT_RTC_CTRL_REG_RTC_READSEL_M,
BIT_RTC_CTRL_REG_RTC_READSEL_M);
if (ret) {
dev_err(&pdev->dev,
"Failed to update RTC control: %d\n", ret);
return ret;
}
ret = regmap_write(rk808->regmap, RK808_RTC_STATUS_REG,
RTC_STATUS_MASK);
if (ret) {
dev_err(&pdev->dev,
"Failed to write RTC status: %d\n", ret);
return ret;
}
/* set init time */
ret = rk808_rtc_readtime(&pdev->dev, &tm);
if (ret) {
dev_err(&pdev->dev, "Failed to read RTC time\n");
return ret;
}
ret = rtc_valid_tm(&tm);
if (ret)
dev_warn(&pdev->dev, "invalid date/time\n");
device_init_wakeup(&pdev->dev, 1);
rk808_rtc->rtc = devm_rtc_device_register(&pdev->dev, "rk808-rtc",
&rk808_rtc_ops, THIS_MODULE);
if (IS_ERR(rk808_rtc->rtc)) {
ret = PTR_ERR(rk808_rtc->rtc);
return ret;
}
rk808_rtc->irq = platform_get_irq(pdev, 0);
if (rk808_rtc->irq < 0) {
if (rk808_rtc->irq != -EPROBE_DEFER)
dev_err(&pdev->dev, "Wake up is not possible as irq = %d\n",
rk808_rtc->irq);
return rk808_rtc->irq;
}
/* request alarm irq of rk808 */
ret = devm_request_threaded_irq(&pdev->dev, rk808_rtc->irq, NULL,
rk808_alarm_irq, 0,
"RTC alarm", rk808_rtc);
if (ret) {
dev_err(&pdev->dev, "Failed to request alarm IRQ %d: %d\n",
rk808_rtc->irq, ret);
}
return ret;
}
示例11: meson_pinconf_set
static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
unsigned long *configs, unsigned num_configs)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_bank *bank;
enum pin_config_param param;
unsigned int reg, bit;
int i, ret;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
ret = regmap_update_bits(pc->reg_pull, reg,
BIT(bit), 0);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_UP:
dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
®, &bit);
ret = regmap_update_bits(pc->reg_pullen, reg,
BIT(bit), BIT(bit));
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
ret = regmap_update_bits(pc->reg_pull, reg,
BIT(bit), BIT(bit));
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
®, &bit);
ret = regmap_update_bits(pc->reg_pullen, reg,
BIT(bit), BIT(bit));
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
ret = regmap_update_bits(pc->reg_pull, reg,
BIT(bit), 0);
if (ret)
return ret;
break;
default:
return -ENOTSUPP;
}
}
return 0;
}
示例12: adau1701_set_dai_fmt
static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
unsigned int serictl = 0x00, seroctl = 0x00;
bool invert_lrclk;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
/* master, 64-bits per sample, 1 frame per sample */
seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
| ADAU1701_SEROCTL_OLF1024;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
invert_lrclk = true;
break;
case SND_SOC_DAIFMT_IB_NF:
invert_lrclk = false;
serictl |= ADAU1701_SERICTL_INV_BCLK;
seroctl |= ADAU1701_SEROCTL_INV_BCLK;
break;
case SND_SOC_DAIFMT_IB_IF:
invert_lrclk = true;
serictl |= ADAU1701_SERICTL_INV_BCLK;
seroctl |= ADAU1701_SEROCTL_INV_BCLK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
serictl |= ADAU1701_SERICTL_LEFTJ;
seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
invert_lrclk = !invert_lrclk;
break;
case SND_SOC_DAIFMT_RIGHT_J:
serictl |= ADAU1701_SERICTL_RIGHTJ_24;
seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
invert_lrclk = !invert_lrclk;
break;
default:
return -EINVAL;
}
if (invert_lrclk) {
seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
serictl |= ADAU1701_SERICTL_INV_LRCLK;
}
adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
return 0;
}
示例13: tps65910_rtc_probe
static int tps65910_rtc_probe(struct platform_device *pdev)
{
struct tps65910 *tps65910 = NULL;
struct tps65910_rtc *tps_rtc = NULL;
int ret;
int irq;
u32 rtc_reg;
tps65910 = dev_get_drvdata(pdev->dev.parent);
tps_rtc = devm_kzalloc(&pdev->dev, sizeof(struct tps65910_rtc),
GFP_KERNEL);
if (!tps_rtc)
return -ENOMEM;
/* Clear pending interrupts */
ret = regmap_read(tps65910->regmap, TPS65910_RTC_STATUS, &rtc_reg);
if (ret < 0)
return ret;
ret = regmap_write(tps65910->regmap, TPS65910_RTC_STATUS, rtc_reg);
if (ret < 0)
return ret;
dev_dbg(&pdev->dev, "Enabling rtc-tps65910.\n");
/* Enable RTC digital power domain */
ret = regmap_update_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_RTC_PWDN_MASK, 0 << DEVCTRL_RTC_PWDN_SHIFT);
if (ret < 0)
return ret;
rtc_reg = TPS65910_RTC_CTRL_STOP_RTC;
ret = regmap_write(tps65910->regmap, TPS65910_RTC_CTRL, rtc_reg);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, tps_rtc);
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
dev_warn(&pdev->dev, "Wake up is not possible as irq = %d\n",
irq);
return -ENXIO;
}
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
tps65910_rtc_interrupt, IRQF_TRIGGER_LOW | IRQF_EARLY_RESUME,
dev_name(&pdev->dev), &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "IRQ is not free.\n");
return ret;
}
tps_rtc->irq = irq;
device_set_wakeup_capable(&pdev->dev, 1);
tps_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&tps65910_rtc_ops, THIS_MODULE);
if (IS_ERR(tps_rtc->rtc)) {
ret = PTR_ERR(tps_rtc->rtc);
dev_err(&pdev->dev, "RTC device register: err %d\n", ret);
return ret;
}
return 0;
}
示例14: max98504_probe
static int max98504_probe(struct max98504_priv *max98504)
{
struct max98504_pdata *pdata = max98504->pdata;
struct max98504_cfg_data *cfg_data = &pdata->cfg_data;
u8 regval;
int ret;
unsigned int value;
msg_maxim("\n");
max98504_reset(max98504);
ret = regmap_read(max98504->regmap, MAX98504_REG_7FFF_REV_ID, &value);
if (ret < 0) {
pr_err("Failed to read device revision: %d\n",
ret);
goto err_access;
}
msg_maxim("REV ID=0x%x\n", value);
if (!pdata) {
pr_err("No platform data\n");
return ret;
}
/* Configure Rx Mode */
if (pdata->rx_mode == MODE_RX_PCM) {
regval = 0;
if (cfg_data->rx_dither_en)
regval |= M98504_PCM_DSP_CFG_RX_DITH_EN_MASK;
if (cfg_data->rx_flt_mode)
regval |= M98504_PCM_DSP_CFG_RX_FLT_MODE_MASK;
regmap_update_bits(max98504->regmap,
MAX98504_REG_25_PCM_DSP_CONFIG,
M98504_PCM_DSP_CFG_RX_DITH_EN_MASK|\
M98504_PCM_DSP_CFG_RX_FLT_MODE_MASK,
regval);
regmap_write(max98504->regmap,
MAX98504_REG_20_PCM_RX_ENABLES, (u8)cfg_data->rx_ch_en);
} else if (pdata->rx_mode == MODE_RX_PDM0 || \
pdata->rx_mode == MODE_RX_PDM1) {
regmap_write(max98504->regmap,
MAX98504_REG_33_PDM_RX_ENABLE, M98504_PDM_RX_EN_MASK);
} else {
regmap_write(max98504->regmap,
MAX98504_REG_20_PCM_RX_ENABLES, 0);
regmap_write(max98504->regmap,
MAX98504_REG_33_PDM_RX_ENABLE, 0);
}
regmap_write(max98504->regmap,
MAX98504_REG_35_SPEAKER_SOURCE_SELECT,
(u8) (M98504_SPK_SRC_SEL_MASK & pdata->rx_mode));
/* Configure Tx Mode */
if (pdata->tx_mode == MODE_TX_PCM) {
regval = 0;
if (cfg_data->tx_dither_en)
regval |= M98504_PCM_DSP_CFG_TX_DITH_EN_MASK;
if (cfg_data->meas_dc_block_en)
regval |= M98504_PCM_DSP_CFG_MEAS_DCBLK_EN_MASK;
regmap_update_bits(max98504->regmap,
MAX98504_REG_25_PCM_DSP_CONFIG,
M98504_PCM_DSP_CFG_TX_DITH_EN_MASK|\
M98504_PCM_DSP_CFG_MEAS_DCBLK_EN_MASK, regval);
regmap_write(max98504->regmap,
MAX98504_REG_21_PCM_TX_ENABLES, (u8)cfg_data->tx_ch_en);
regmap_write(max98504->regmap,
MAX98504_REG_22_PCM_TX_HIZ_CONTROL,
(u8)cfg_data->tx_hiz_ch_en);
regmap_write(max98504->regmap,
MAX98504_REG_23_PCM_TX_CHANNEL_SOURCES,
(u8)cfg_data->tx_ch_src);
} else {
regmap_write(max98504->regmap,
MAX98504_REG_30_PDM_TX_ENABLES, (u8)cfg_data->tx_ch_en);
regmap_write(max98504->regmap,
MAX98504_REG_31_PDM_TX_HIZ_CONTROL,
(u8)cfg_data->tx_hiz_ch_en);
regmap_write(max98504->regmap,
MAX98504_REG_32_PDM_TX_CONTROL,
(u8)cfg_data->tx_ch_src);
}
regmap_write(max98504->regmap,
MAX98504_REG_36_MEASUREMENT_ENABLES,
M98504_MEAS_I_EN_MASK | M98504_MEAS_V_EN_MASK);
/* Brownout Protection */
regmap_write(max98504->regmap,
MAX98504_REG_16_PVDD_BROWNOUT_ENABLE, 0x1);
regmap_write(max98504->regmap,
MAX98504_REG_17_PVDD_BROWNOUT_CONFIG_1, 0x33);
regmap_write(max98504->regmap,
MAX98504_REG_18_PVDD_BROWNOUT_CONFIG_2, 0x0a);
regmap_write(max98504->regmap,
MAX98504_REG_19_PVDD_BROWNOUT_CONFIG_3, 0xff);
regmap_write(max98504->regmap,
//.........这里部分代码省略.........
示例15: fsl_esai_divisor_cal
/**
* This function is used to calculate the divisors of psr, pm, fp and it is
* supposed to be called in set_dai_sysclk() and set_bclk().
*
* @ratio: desired overall ratio for the paticipating dividers
* @usefp: for HCK setting, there is no need to set fp divider
* @fp: bypass other dividers by setting fp directly if fp != 0
* @tx: current setting is for playback or capture
*/
static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
bool usefp, u32 fp)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
maxfp = usefp ? 16 : 1;
if (usefp && fp)
goto out_fp;
if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
2 * 8 * 256 * maxfp);
return -EINVAL;
} else if (ratio % 2) {
dev_err(dai->dev, "the raio must be even if using upper divider\n");
return -EINVAL;
}
ratio /= 2;
psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
/* Set the max fluctuation -- 0.1% of the max devisor */
savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
/* Find the best value for PM */
for (i = 1; i <= 256; i++) {
for (j = 1; j <= maxfp; j++) {
/* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
prod = (psr ? 1 : 8) * i * j;
if (prod == ratio)
sub = 0;
else if (prod / ratio == 1)
sub = prod - ratio;
else if (ratio / prod == 1)
sub = ratio - prod;
else
continue;
/* Calculate the fraction */
sub = sub * 1000 / ratio;
if (sub < savesub) {
savesub = sub;
pm = i;
fp = j;
}
/* We are lucky */
if (savesub == 0)
goto out;
}
}
if (pm == 999) {
dev_err(dai->dev, "failed to calculate proper divisors\n");
return -EINVAL;
}
out:
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
psr | ESAI_xCCR_xPM(pm));
out_fp:
/* Bypass fp if not being required */
if (maxfp <= 1)
return 0;
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
return 0;
}