本文整理汇总了C++中reg_write函数的典型用法代码示例。如果您正苦于以下问题:C++ reg_write函数的具体用法?C++ reg_write怎么用?C++ reg_write使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了reg_write函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: gs_set_offset
static int gs_set_offset( void )
{
int ret;
ret = reg_write(this_gs_data,GS_ADI_REG_OFSX,0x03); /* set OFSX offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSX failed\n");
}
ret = reg_write(this_gs_data,GS_ADI_REG_OFSY,0x03); /* set OFSY offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSY failed\n");
}
ret = reg_write(this_gs_data,GS_ADI_REG_OFSZ,0x0B); /* set OFSZ offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSZ failed\n");
}
return ret;
}
示例2: mv88e6060_phy_write
static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
int addr;
addr = mv88e6060_port_to_phy_addr(port);
if (addr == -1)
return 0xffff;
return reg_write(ds, addr, regnum, val);
}
示例3: gs_resume
static int gs_resume(struct i2c_client *client)
{
struct gs_data *gs = i2c_get_clientdata(client);
reg_write(gs, GS_ST_REG_CTRL1, GS_ST_CTRL1_PD|
GS_ST_CTRL1_Zen|
GS_ST_CTRL1_Yen|
GS_ST_CTRL1_Xen); /* enable abs int */
reg_write(gs, GS_ST_REG_CTRL3, GS_INTMODE_DATA_READY);/*active mode*/
if (!gs->use_irq)
hrtimer_start(&gs->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
else
enable_irq(client->irq);
return 0;
}
示例4: snd_ak4117_reinit
void snd_ak4117_reinit(struct ak4117 *chip)
{
unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
del_timer(&chip->timer);
chip->init = 1;
/* bring the chip to reset state and powerdown state */
reg_write(chip, AK4117_REG_PWRDN, 0);
udelay(200);
/* release reset, but leave powerdown */
reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
udelay(200);
for (reg = 1; reg < 5; reg++)
reg_write(chip, reg, chip->regmap[reg]);
/* release powerdown, everything is initialized now */
reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
chip->init = 0;
chip->timer.expires = 1 + jiffies;
add_timer(&chip->timer);
}
示例5: timer_inc
//This function is called on all IRQ interrupts
void timer_inc(void)
{
//increment the number of the timer ticks
++num_timer_tick;
//reset the OSSR[M0]bit
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
osmr_count += CLOCKS_PER_TICK;
//reset the OSCR to 0
reg_write(OSTMR_OSMR_ADDR(0), osmr_count);
}
示例6: top_write_pin
static void top_write_pin(int pin, TOP_PINMUX_t reg)
{
switch (pin) {
case 4:
reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
break;
case 5:
reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
break;
case 7:
reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
break;
case 8:
reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
break;
case 10:
case 11:
case 12:
case 13:
case 14:
case 15:
case 16:
reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
((pin - 10) * 4), reg.reg);
break;
default:
reg_write(TOP_BASE + (pin * 4), reg.reg);
break;
}
}
示例7: dcm_armcore
int dcm_armcore(ENUM_ARMCORE_DCM mode)
{
if (mode == ARMCORE_DCM_OFF) {
//swithc to mode 2, and turn wfi/wfe-enable off
reg_write(INFRA_TOPCKGEN_DCMDBC,
and(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0))); //disable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(0x3<<1), (0<<1))); //disable wfi/wfe-en
return 0;
}
if (mode == ARMCORE_DCM_MODE2) {
//switch to mode 2
reg_write(INFRA_TOPCKGEN_DCMDBC,
and(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0))); //disable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(3<<1), (3<<1)));
// OVERRIDE pll mux and clkdiv !!
dcm_armcore_pll_clkdiv(1, (3<<3)|(0)); // armpll, 6/6
}
else if (mode == ARMCORE_DCM_MODE1) {
//switch to mode 1, and mode 2 off
reg_write(INFRA_TOPCKGEN_DCMDBC,
aor(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0), (1<<0))); //enable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(3<<1), (0<<1)));
}
return 0;
}
示例8: irq_handler
void irq_handler(void) {
disable_interrupts();
irq_time ++;
dev_update(irq_time);
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
reg_write(OSTMR_OSCR_ADDR, TIMER_CLEAR);
/* Wait for timer to reset */
while(((volatile unsigned)reg_read(INT_ICPR_ADDR) >>INT_OSTMR_0) & 0x1);
dispatch_save();
}
示例9: timer_init
/* in this function, we configure the OS timer register */
void timer_init(void)
{
//size_t num_clock;
//calculate the clocks for a time unit: 10ms for now
//Will change to the following line if set to 10ms
//num_clock = OSTMR_FREQ/OS_TICKS_PER_SEC;
//num_clock = OSTMR_FREQ/(S_TO_MS/MS_PER_TICK);
osmr_count = CLOCKS_PER_TICK;
//init OSCR to 0
reg_write(OSTMR_OSCR_ADDR, 0);
//init OSMR0 to num_clock
reg_write(OSTMR_OSMR_ADDR(0), osmr_count);
/*
* set OIER last bit 1 to enbale match between OSCR
* and OSMR0 to assert OSSR[M0]
*/
reg_set(OSTMR_OIER_ADDR, OSTMR_OIER_E0);
}
示例10: aac_sensor_probe
/*
* platform operation relate functions
*/
static int aac_sensor_probe(struct i2c_client *client,const struct i2c_device_id *idp)
{
struct sensor_device *dev;
u8 val;
dev=&sensor_priv;
/* initualize wait queue */
init_completion(&dev->data_comp);
INIT_DELAYED_WORK(&dev->data_work,aac_sensor_work);
if(sensor_interrupt_init()){
sensor_error("Fail to config gpio port\n");
return -1;
}
if(request_irq(IRQ_EINT5, aac_sensor_irq,IRQF_DISABLED,"aac_sensor",dev)){
sensor_error("Fail to request gpio interrupt\n");
return -1;
}
sensor_interrupt_disable();
sensor_interrupt_clear();
reg_write(client,MMA_MODE,0); //Make 7660 enter standby mode to set registers
reg_write(client,MMA_SPCNT,0xff);
reg_write(client,MMA_INTSU,MMA_INT_FB|MMA_INT_PL/*|MMA_INT_PD*/);
val=0;
SET_BITS(val,MMA_SR_AMSR,AMSR_RATE_128);
SET_BITS(val,MMA_SR_AWSR,AWSR_RATE_32);
SET_BITS(val,MMA_SR_FILT,FILT_DISABLE);
reg_write(client,MMA_SR,val);
val=0;
SET_BITS(val,MMA_PDET_PDTH,2);
SET_BITS(val,MMA_PDET_XDA,1);
SET_BITS(val,MMA_PDET_YDA,1);
SET_BITS(val,MMA_PDET_ZDA,1);
reg_write(client,MMA_PDET,val);
reg_write(client,MMA_PD,0x1f);
reg_write(client,MMA_MODE,
MMA_MODE_MODE|MMA_MODE_AWE| //active
MMA_MODE_ASE/*|MMA_MODE_SCPS*/| //auto wake/suspend
MMA_MODE_IPP); //int active low
sensor_priv.client=client;
//i2c_set_clientdata(client, nas_priv);
return 0;
}
示例11: ak881x_s_register
static int ak881x_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (reg->reg > 0x26)
return -EINVAL;
if (reg_write(client, reg->reg, reg->val) < 0)
return -EIO;
return 0;
}
示例12: mv_xor_ctrl_set
/*
* mv_xor_ctrl_set - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
* NOTE:
* This function does not modify the Operation_mode field of control register.
*/
int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
{
u32 old_value;
/* update the XOR Engine [0..1] Configuration Registers (XEx_c_r) */
old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) &
XEXCR_OPERATION_MODE_MASK;
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
xor_ctrl |= old_value;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
return MV_OK;
}
示例13: hw_r5_enable_clock
static void hw_r5_enable_clock(struct zynqmp_r5_rproc_pdata *pdata)
{
u32 tmp;
pr_debug("%s: mode: %d\n", __func__, pdata->rpu_mode);
tmp = reg_read(pdata->crl_apb_base, CPU_R5_CTRL_OFFSET);
if (!(tmp & RPU_CLKACT_MASK)) {
tmp |= RPU_CLKACT_MASK;
reg_write(pdata->crl_apb_base, CPU_R5_CTRL_OFFSET, tmp);
/* Give some delay for clock to propogate */
udelay(500);
}
}
示例14: hw_clear_ipi
/*
* TODO: Update HW ipi operation when the driver is ready
*/
static irqreturn_t hw_clear_ipi(struct zynqmp_r5_rproc_pdata *pdata)
{
u32 ipi_reg = 0;
pr_debug("%s: irq issuer %08x clear IPI\n", __func__,
pdata->ipi_dest_mask);
ipi_reg = reg_read(pdata->ipi_base, ISR_OFFSET);
if (ipi_reg & pdata->ipi_dest_mask) {
reg_write(pdata->ipi_base, ISR_OFFSET, pdata->ipi_dest_mask);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
示例15: gs_st_open
static int gs_st_open(struct inode *inode, struct file *file)
{
reg_read(this_gs_data, GS_ST_REG_STATUS ); /* read status */
reg_write(this_gs_data, GS_ST_REG_CTRL1, GS_ST_CTRL1_PD|
GS_ST_CTRL1_Zen|
GS_ST_CTRL1_Yen|
GS_ST_CTRL1_Xen);
reg_write(this_gs_data, GS_ST_REG_CTRL3, GS_INTMODE_DATA_READY);
reg_read(this_gs_data, GS_ST_REG_OUT_X ); /* read X */
reg_read(this_gs_data, GS_ST_REG_OUT_Y ); /* read Y */
reg_read(this_gs_data, GS_ST_REG_OUT_Z ); /* read Z*/
if (this_gs_data->use_irq)
enable_irq(this_gs_data->client->irq);
else
hrtimer_start(&this_gs_data->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
return nonseekable_open(inode, file);
}