C++ read_c0_cause函数代码示例

int ath_be_handler(struct pt_regs *regs, int is_fixup)
{
#ifdef CONFIG_MACH_AR934x
	printk("ath data bus error: cause 0x%x epc 0x%x\nrebooting...", read_c0_cause(), read_c0_epc());
	ath_restart(NULL);
#else
	printk("ath data bus error: cause %#x\n", read_c0_cause());
#endif
	return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned long pending;

	pending = read_c0_status() & read_c0_cause() & ST0_IM;

	if (pending & STATUSF_IP7)
		do_IRQ(AR71XX_CPU_IRQ_TIMER);

	else if (pending & STATUSF_IP2)
		ip2_handler();

	else if (pending & STATUSF_IP4)
		do_IRQ(AR71XX_CPU_IRQ_GE0);

	else if (pending & STATUSF_IP5)
		do_IRQ(AR71XX_CPU_IRQ_GE1);

	else if (pending & STATUSF_IP3)
		ip3_handler();

	else if (pending & STATUSF_IP6)
		ar71xx_misc_irq_dispatch();

	else
		spurious_interrupt();
}

irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
{
	const int r2 = cpu_has_mips_r2;
	struct clock_event_device *cd;
	int cpu = smp_processor_id();

	/*
                  
                                                              
                                                                
                                                     
  */
	if (handle_perf_irq(r2))
		goto out;

	/*
                                                                     
                                                                 
                                                            
  */
	if (!r2 || (read_c0_cause() & (1 << 30))) {
		/*                               */
		write_c0_compare(read_c0_compare());
		cd = &per_cpu(mips_clockevent_device, cpu);
		cd->event_handler(cd);
	}

out:
	return IRQ_HANDLED;
}

/*! @brief the interrupt exception service function.
 *	@details The \cplat_irq_dispatch() function is the interrupt exception
 *	service function called. When an exception is set and the exception
 *	code indicates an interrupt (0x00).
 */
asmlinkage void plat_irq_dispatch(
	struct pt_regs			*regs	/*!< registers of the interrupted task */
)
{
	/* Get the current pending interrupt status */
	unsigned long	pending = read_c0_cause() & read_c0_status();

	/*!	@note Clear all pending interrupts before dispatching. The
		interrupt information structure will call the "end" function
		from the do_IRQ function that should re-enable the specific
		interrupt while completing the interrupt handling (see
		irq_chip structure). */
	/* Disable all MIPS active pending interrupts */
	clear_c0_status(pending);
	/* These are the interrupts that are to be dispatched */
	if( pending & (STATUSF_IP7|STATUSF_IP2) ) {
		/* Dispatch timer interrupt (HW INT#5/IP7)  */
		if (pending & STATUSF_IP7)
			brcm_mips_int7_dispatch(regs);
		/* Dispatch shared interrupt (HW INT#0/IP2)  */
		if (pending & STATUSF_IP2)
			brcm_mips_int2_dispatch(regs);
		/* Return following the successful interrupt exception handling */
		return;
	}
	/* Other interrupts are unhandled and treated as spurious interrupts */
	spurious_interrupt(regs);
}

void
brcm_irq_dispatch(struct pt_regs *regs)
{
	u32 cause;

	cause = read_c0_cause() &
		read_c0_status() &
		CAUSEF_IP;

#ifdef CONFIG_KERNPROF
	change_c0_status(cause | 1, 1);
#else
	clear_c0_status(cause);
#endif

	if (cause & CAUSEF_IP7)
		do_IRQ(7, regs);
	if (cause & CAUSEF_IP2)
		do_IRQ(2, regs);
	if (cause & CAUSEF_IP3)
		do_IRQ(3, regs);
	if (cause & CAUSEF_IP4)
		do_IRQ(4, regs);
	if (cause & CAUSEF_IP5)
		do_IRQ(5, regs);
	if (cause & CAUSEF_IP6)
		do_IRQ(6, regs);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (pending & CAUSEF_IP7)	
	{
		do_IRQ(M36_IRQ_TIMER);
	}
	else if ((pending & CAUSEF_IP3) || (pending & CAUSEF_IP2))
	{
		sys_irqdispatch();
	}
	else
	{
#ifdef CONFIG_ENABLE_RPC
		{
			unsigned long rpc_status;

			rpc_status = *(volatile unsigned char *)(sys_rpc_addr);
			rpc_status &= sys_rpc_mask;
			
			if(rpc_status & sys_rpc_irq1_mask)
				do_IRQ(71);
			
			if(rpc_status & sys_rpc_irq2_mask)
				do_IRQ(70);	
		}
#endif
		spurious_interrupt();
	}
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned long pending;

	pending = read_c0_status() & read_c0_cause() & ST0_IM;

	if (pending & STATUSF_IP7)
		do_IRQ(ATH79_CPU_IRQ(7));

	else if (pending & STATUSF_IP2)
		ath79_ip2_handler();

	else if (pending & STATUSF_IP4)
		do_IRQ(ATH79_CPU_IRQ(4));

	else if (pending & STATUSF_IP5)
		do_IRQ(ATH79_CPU_IRQ(5));

	else if (pending & STATUSF_IP3)
		ath79_ip3_handler();

	else if (pending & STATUSF_IP6)
		do_IRQ(ATH79_CPU_IRQ(6));

	else
		spurious_interrupt();
}

irqreturn_t smtc_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	int cpu = smp_processor_id();
	int vpflags;

	if (read_c0_cause() & (1 << 30)) {
		/* If timer interrupt, make it de-assert */
		write_c0_compare (read_c0_count() - 1);

                vpflags = dvpe();
                clear_c0_cause(0x100<<7);
                evpe(vpflags);

		/*
		 * There are things we only want to do once per tick
		 * in an "MP" system.   One TC of each VPE will take
		 * the actual timer interrupt.  The others will get
		 * timer broadcast IPIs. We use whoever it is that takes
		 * the tick on VPE 0 to run the full timer_interrupt().
		 */
		if (cpu_data[cpu].vpe_id == 0) {
				timer_interrupt(irq, NULL, regs);
				smtc_timer_broadcast(cpu_data[cpu].vpe_id);

		} else {
			write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
			local_timer_interrupt(irq, dev_id, regs);
			smtc_timer_broadcast(cpu_data[cpu].vpe_id);
		}
	}

	return IRQ_HANDLED;
}

static int
tx4939_proc_show_cp0(char *sysbuf, char **start, off_t off,
		     int count, int *eof, void *data)
{
	int len = 0;
	len += sprintf(sysbuf + len, "INDEX   :0x%08x\n", read_c0_index());
	len += sprintf(sysbuf + len, "ENTRYLO0:0x%08lx\n", read_c0_entrylo0());
	len += sprintf(sysbuf + len, "ENTRYLO1:0x%08lx\n", read_c0_entrylo1());
	len += sprintf(sysbuf + len, "CONTEXT :0x%08lx\n", read_c0_context());
	len += sprintf(sysbuf + len, "PAGEMASK:0x%08x\n", read_c0_pagemask());
	len += sprintf(sysbuf + len, "WIRED   :0x%08x\n", read_c0_wired());
	len += sprintf(sysbuf + len, "COUNT   :0x%08x\n", read_c0_count());
	len += sprintf(sysbuf + len, "ENTRYHI :0x%08lx\n", read_c0_entryhi());
	len += sprintf(sysbuf + len, "COMPARE :0x%08x\n", read_c0_compare());
	len += sprintf(sysbuf + len, "STATUS  :0x%08x\n", read_c0_status());
	len += sprintf(sysbuf + len, "CAUSE   :0x%08x\n", read_c0_cause());
	len += sprintf(sysbuf + len, "PRId    :0x%08x\n", read_c0_prid());
	len += sprintf(sysbuf + len, "CONFIG  :0x%08x\n", read_c0_config());
	len += sprintf(sysbuf + len, "XCONTEXT:0x%08lx\n", read_c0_xcontext());
	len += sprintf(sysbuf + len, "TagLo   :0x%08x\n", read_c0_taglo());
	len += sprintf(sysbuf + len, "TagHi   :0x%08x\n", read_c0_taghi());
	len += sprintf(sysbuf + len, "ErrorEPC:0x%08lx\n", read_c0_errorepc());
	*eof = 1;
	return len;
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int pending;

	/*
	 * What a pain. We have to be really careful saving the upper 32 bits
	 * of any * register across function calls if we don't want them
	 * trashed--since were running in -o32, the calling routing never saves
	 * the full 64 bits of a register across a function call.  Being the
	 * interrupt handler, we're guaranteed that interrupts are disabled
	 * during this code so we don't have to worry about random interrupts
	 * blasting the high 32 bits.
	 */

	pending = read_c0_cause() & read_c0_status() & ST0_IM;

	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	else if (pending & CAUSEF_IP4)
		do_IRQ(K_INT_TIMER_0 + cpu); 	/* sb1250_timer_interrupt() */

#ifdef CONFIG_SMP
	else if (pending & CAUSEF_IP3)
		sb1250_mailbox_interrupt();
#endif

	else if (pending & CAUSEF_IP2)
		dispatch_ip2();
	else
		spurious_interrupt();
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned long pending;

	pending = read_c0_status() & read_c0_cause() & ST0_IM;

	if (pending & STATUSF_IP7)
		do_IRQ(AR71XX_CPU_IRQ_TIMER);

#ifdef CONFIG_PCI
	else if (pending & STATUSF_IP2)
		ar71xx_pci_irq_dispatch();
#endif

	else if (pending & STATUSF_IP4)
		do_IRQ(AR71XX_CPU_IRQ_GE0);

	else if (pending & STATUSF_IP5)
		do_IRQ(AR71XX_CPU_IRQ_GE1);

	else if (pending & STATUSF_IP3)
		do_IRQ(AR71XX_CPU_IRQ_USB);

	else if (pending & STATUSF_IP6)
		ar71xx_misc_irq_dispatch();

	else
		spurious_interrupt();
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cause = read_c0_cause();
	unsigned int status = read_c0_status();
	unsigned int pending = cause & status;

	if (pending & STATUSF_IP7) {
		do_IRQ(7);
	} else if (pending & STATUSF_IP2) {
#ifdef CONFIG_HYPERTRANSPORT
		ll_ht_smp_irq_handler(2);
#else
		do_IRQ(2);
#endif
	} else if (pending & STATUSF_IP3) {
		do_IRQ(3);
	} else if (pending & STATUSF_IP4) {
		do_IRQ(4);
	} else if (pending & STATUSF_IP5) {
#ifdef CONFIG_SMP
		titan_mailbox_irq();
#else
		do_IRQ(5);
#endif
	} else if (pending & STATUSF_IP6) {
		do_IRQ(4);
	}
}

/*
 * Dispatch interrupts. 
 * XXX: This currently does not prioritize except in calling order. Eventually
 * there should perhaps be a static map which defines, the IPs to be masked for
 * a given IP.
 */
void
ar7240_irq_dispatch(struct pt_regs *regs)
{
	int pending = read_c0_status() & read_c0_cause();

	if (pending & CAUSEF_IP7) 
        do_IRQ(AR7240_CPU_IRQ_TIMER, regs);

    else if (pending & CAUSEF_IP2) 
        ar7240_dispatch_pci_intr(regs);

    else if (pending & CAUSEF_IP4) 
        do_IRQ(AR7240_CPU_IRQ_GE0, regs);

    else if (pending & CAUSEF_IP5) 
        do_IRQ(AR7240_CPU_IRQ_GE1, regs);

    else if (pending & CAUSEF_IP3) 
        do_IRQ(AR7240_CPU_IRQ_USB, regs);

    else if (pending & CAUSEF_IP6) 
        ar7240_dispatch_misc_intr(regs);

    /*
     * Some PCI devices are write to clear. These writes are posted and might
     * require a flush (r8169.c e.g.). Its unclear what will have more 
     * performance impact - flush after every interrupt or taking a few
     * "spurious" interrupts. For now, its the latter.
     */
    /*else 
        printk("spurious IRQ pending: 0x%x\n", pending);*/
}

static void
tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
{
	unsigned long val = 0;

	switch (cp0_reg) {
	case CCP0_STATUS:
		val = read_c0_status();
		break;

	case CCP0_CAUSE:
		val = read_c0_cause();
		break;

	}

	val &= (~clr_bits);
	val |= (set_bits);

	switch (cp0_reg) {
	case CCP0_STATUS:{
			write_c0_status(val);
			break;
		}
	case CCP0_CAUSE:{
			write_c0_cause(val);
			break;
		}
	}

	return;
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cause = read_c0_cause();
	unsigned int pending;
	int cpuid = smp_processor_id();
	unsigned long flags;
	pending = cause & read_c0_status() & ST0_IM;
#ifdef CONFIG_SMP
	if(pending & CAUSEF_IP3) {
		ipr_spinlock(flags);
		//irq_intc_ctrlmask_affinity(cpuid,1);
		response_cpu_busy |= 1 << cpuid;
		ipr_spinunlock(flags);

		jzsoc_mbox_interrupt(cpuid);

		ipr_spinlock(flags);
		response_cpu_busy &= ~(1 << cpuid);
		//irq_intc_ctrlmask_affinity(cpuid,0);
		ipr_spinunlock(flags);
	}
#endif
	if (cause & CAUSEF_IP4) {
		do_IRQ(IRQ_OST);
	}

	if(pending & CAUSEF_IP2) {
		intc_irq_dispatch(cpuid);
	}
}