C++ putreg16函数代码示例

int efm32_rtc_cancelalarm(void)
{
  irqstate_t flags;
  int ret = -ENODATA;

  if (g_alarmcb != NULL)
    {
      /* Cancel the global callback function */

      g_alarmcb = NULL;

      /* Unset the alarm */

      flags = irqsave();
      stm32_rtc_beginwr();
      putreg16(0xffff, STM32_RTC_ALRH);
      putreg16(0xffff, STM32_RTC_ALRL);
      stm32_rtc_endwr();
      irqrestore(flags);

      ret = OK;
    }

  return ret;
}

void up_irqinitialize(void)
{
  /* Prepare hardware */

  calypso_exceptions_install();
  current_regs = NULL;

  /* Switch to internal ROM */

  calypso_bootrom(1);

  /* Set default priorities */

  set_default_priorities();

  /* Mask all interrupts off */

  putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
  putreg16(0xffff, IRQ_REG(MASK_IT_REG2));

  /* clear all pending interrupts */
  putreg16(0, IRQ_REG(IT_REG1));
  putreg16(0, IRQ_REG(IT_REG2));

  /* Enable interrupts globally to the ARM core */

#ifndef CONFIG_SUPPRESS_INTERRUPTS
  irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}

void up_ack_irq(int irq)
{
  /* Acknowlege the interrupt by setting the corresponding bit in the
   * IRQ status register.
   */

  if (irq < 16)
    {
      /* Set the associated status bit to clear the interrupt */

      putreg16((1 << irq), DM320_INTC_IRQ0);
    }
  else if (irq < 32)
    {
      /* Set the associated status bit to clear the interrupt  */

      putreg16((1 << (irq-16)), DM320_INTC_IRQ1);
    }
  else
    {
      /* Set the associated status bit to clear the interrupt */

      putreg16((1 << (irq-32)), DM320_INTC_IRQ2);
    }
}

void wdog_enable(int on)
{
	if (!on) {
		putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
		putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
	}
}

static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power)
{
  DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);

  /* Set new power level */

  if (power > 0)
    {
      uint32_t duty;

      /* Calculate the new backlight duty.  It is a fraction of the timer
       * period based on the ration of the current power setting to the
       * maximum power setting.
       */

      duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / CONFIG_LCD_MAXPOWER;
      if (duty >= LCD_BL_TIMER_PERIOD)
        {
          duty = LCD_BL_TIMER_PERIOD - 1;
        }

      putreg16((uint16_t)duty, STM32_TIM3_CCR2);
    }
  else
    {
      putreg16((uint16_t)0, STM32_TIM3_CCR2);
    }
}

static void lcd_wrdata(uint8_t data)
{
  /* Make sure that the LCD is available */

  lcd_waitbusy();

  /* Select DB0-15 as outputs (only DB-0-7 are actually used) */

  putreg16(0, PIC32MX_IOPORTE_TRIS);

  /* Set up to write the data */

  pic32mx_gpiowrite(GPIO_LCD_RS, true);    /* Select data */
  pic32mx_gpiowrite(GPIO_LCD_RW, false);   /* Select write */
  lcd_shortdelay(2);

  pic32mx_gpiowrite(GPIO_LCD_E, true);     /* Enable transfer */
  lcd_shortdelay(1);

  /* Write the data to the LCD */

  putreg16(data, PIC32MX_IOPORTE_PORT);    /* Write the data */
  lcd_shortdelay(1);
  pic32mx_gpiowrite(GPIO_LCD_E, false);
}

void spi_init(void)
{
  putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
           SPI_REG(REG_SET1));

  putreg16(0x0001, SPI_REG(REG_SET2));
}

void up_enable_irq(int irq)
{
  /* Enable the interrupt by setting the corresponding bit in
   * the IRQ enable register.
   */

  if (irq < 16)
    {
      /* IRQs0-15 are controlled by the IRQ0 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT0) | (1 << irq)), DM320_INTC_EINT0);
    }
  else if (irq < 32)
    {
      /* IRQs16-31 are controlled by the IRQ1 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT1) | (1 << (irq-16))), DM320_INTC_EINT1);
    }
  else
    {
      /* IRQs32- are controlled by the IRQ2 enable register
       * Set the associated bit to enable the interrupt
       */

      putreg16((getreg16(DM320_INTC_EINT2) | (1 << (irq-32))), DM320_INTC_EINT2);
    }
}

int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
{
  uint16_t tmp = 0;

  if (bitlen <= 0 || bitlen > 16)
      return -1;

  if (cs < 0 || cs > 4)
      return -1;

  /* FIXME uwire_init always selects CS0 for now */

  dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);

  /* select the chip */

  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  if (dout)
    {
      if (bitlen <= 8)
          tmp = *(uint8_t *)dout;
      else if (bitlen <= 16)
          tmp = *(uint16_t *)dout;

      tmp <<= 16 - bitlen; /* align to MSB */
      putreg16(tmp, UWIRE_REG(REG_DATA));
      dbg(", data_out=0x%04hx", tmp);
    }

  tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
        (din  ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
         UWIRE_CSR_START;
  putreg16(tmp, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  if (din)
    {
      _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);

      tmp = getreg16(UWIRE_REG(REG_DATA));
      dbg(", data_in=0x%08x", tmp);

      if (bitlen <= 8)
          *(uint8_t *)din = tmp & 0xff;
      else if (bitlen <= 16)
          *(uint16_t *)din = tmp & 0xffff;
    }

  /* unselect the chip */

  putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);

  dbg(")\n");

  return 0;
}

void wdog_reset(void)
{
	// enable watchdog
	putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
	// force expiration
	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
}

void uwire_init(void)
{
  putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));

  /* FIXME only init CS0 for now */

  putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
           UWIRE_REG(UWIRE_CSn_REG(0)));
  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
  _uwire_wait(UWIRE_CSR_CSRB, 0);
}

void wdog_reset(void)
{
  /* Enable watchdog */

  putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));

  /* Force expiration */

  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
}

static void dm320_disable(void)
{
  /* Disable all planes */

  gvdbg("Inactivate OSD:\n");

  putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
  putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */
  putreg16(0, DM320_OSD_RECTCUR);   /* Rectangular cursor mode = 0 (1:active) */

  gvdbg("DM320_OSD_OSDWIN0MD:   %04x\n", getreg16(DM320_OSD_OSDWIN0MD));
  gvdbg("DM320_OSD_OSDWIN1MD:   %04x\n", getreg16(DM320_OSD_OSDWIN1MD));
  gvdbg("DM320_OSD_RECTCUR:     %04x\n", getreg16(DM320_OSD_RECTCUR));
}

void up_timerinit(void)
{
  uint32_t reload;
 
  up_disable_irq(Z8_IRQ_SYSTIMER);

  /* Write to the timer control register to disable the timer, configure
   * the timer for continuous mode, and set up the pre-scale value for
   * divide by 4.
   */

  putreg8((Z8_TIMERCTL_DIV4|Z8_TIMERCTL_CONT), T0CTL);

  /* Write to the timer high and low byte registers to set a starting
   * count value (this effects only the first pass in continuous mode)
   */

  putreg16(0x0001, T0);

  /* Write to the timer reload register to set the reload value.
   *
   * In continuous mode:
   *
   *   timer_period = reload_value x prescale / system_clock_frequency
   * or
   *   reload_value = (timer_period * system_clock_frequency) / prescale
   *
   * For system_clock_frequency=18.432MHz, timer_period=10mS, and prescale=4,
   * then reload_value=46,080 - OR:
   *
   *   reload_value = system_clock_frequency / 400
   */

   reload = get_freq() / 400;
   putreg16((uint16_t)reload, T0R);

  /* Write to the timer control register to enable the timer and to
   * initiate counting
   */

  putreg8((getreg8(T0CTL)|Z8_TIMERCTL_TEN), T0CTL);

  /* Set the timer priority */

  /* Attach and enable the timer interrupt (leaving at priority 0 */

  irq_attach(Z8_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
  up_enable_irq(Z8_IRQ_SYSTIMER);
}

void sercom_slowclk_configure(int gclkgen)
{
  static bool configured = false;
  uint16_t regval;

  /* Since GCLK_SERCOM_SLOW is shard amongst all SERCOM modules, it should
   * only be configured one time.
   */

  if (!configured)
    {
      /* Set up the SERCOM_GCLK_ID_SLOW clock */

      regval = (SERCOM_GCLK_ID_SLOW << GCLK_CLKCTRL_ID_SHIFT);

      /* Select and disable the SERCOM_GCLK_ID_SLOW generic clock */

      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Wait for clock to become disabled */

      while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);

      /* Select the SERCOM_GCLK_ID_SLOW clock source generator */

      regval |= (uint16_t)gclkgen << GCLK_CLKCTRL_GEN_SHIFT;

      /* Write the new configuration */

      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Enable the GCLK_SERCOM_SLOW generic clock and lock further
       * writes to this GCLK.  When this bit is written, it will lock
       * further writes to the generic clock pointed by the CLKCTRL.ID. The
       * generic clock generator pointed by CLKCTRL.GEN and the GENDIV.DIV
       * will also be locked.
       *
       * We lock the SERCOM slow clock because it is common to all SERCOM modules
       * and, once set, should not be changed again.
       */

      regval |= (/* GCLK_CLKCTRL_WRTLOCK | */ GCLK_CLKCTRL_CLKEN);
      putreg16(regval, SAM_GCLK_CLKCTRL);

      /* Now we are configured */

      configured = true;
    }
}