C++ print_mhz函数代码示例

int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i;
	bd_t *bd = gd->bd;

	print_num("boot_params",	(ulong)bd->bi_boot_params);
	print_num("bi_memstart",	bd->bi_memstart);
	print_num("bi_memsize",		bd->bi_memsize);
	print_num("bi_flashstart",	bd->bi_flashstart);
	print_num("bi_flashsize",	bd->bi_flashsize);
	print_num("bi_flashoffset",	bd->bi_flashoffset);
	print_num("bi_sramstart",	bd->bi_sramstart);
	print_num("bi_sramsize",	bd->bi_sramsize);
	print_num("bi_bootflags",	bd->bi_bootflags);
	print_mhz("cpufreq",		bd->bi_intfreq);
	print_mhz("busfreq",		bd->bi_busfreq);

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
		print_num("DRAM bank",	i);
		print_num("-> start",	bd->bi_dram[i].start);
		print_num("-> size",	bd->bi_dram[i].size);
	}

#if defined(CONFIG_CMD_NET)
	print_eth(0);
	printf("ip_addr     = %s\n", getenv("ipaddr"));
	print_mhz("ethspeed",	    bd->bi_ethspeed);
#endif
	printf("baudrate    = %u bps\n", bd->bi_baudrate);

	return 0;
}

void __init_or_cpufreq s3c2412_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long tmp;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long pclk;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);


	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);

	clk_mpll.rate = fclk;

	tmp = __raw_readl(S3C2410_CLKDIVN);

	

	hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
	hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
	pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);

	

	printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

void __init_or_cpufreq s3c2443_setup_clocks(void)
{
	unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long pll;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long pclk;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	pll = s3c2443_get_mpll(mpllcon, xtal);
	clk_msysclk.rate = pll;

	fclk = pll / s3c2443_fclk_div(clkdiv0);
	hclk = s3c2443_prediv_getrate(&clk_prediv);
	hclk /= s3c2443_get_hdiv(clkdiv0);
 	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);

	s3c24xx_setup_clocks(fclk, hclk, pclk);

	printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
	       (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
	       print_mhz(pll), print_mhz(fclk),
	       print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

void __init_or_cpufreq s3c2412_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long tmp;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long pclk;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	/* now we've got our machine bits initialised, work out what
	 * clocks we've got */

	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);

	clk_mpll.rate = fclk;

	tmp = __raw_readl(S3C2410_CLKDIVN);

	/* work out clock scalings */

	hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
	hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
	pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);

	/* print brieft summary of clocks, etc */

	printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

void __init s3c2410_map_io(struct map_desc *mach_desc, int size)
{
	unsigned long tmp;

	/* register our io-tables */

	iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
	iotable_init(mach_desc, size);

	/* now we've got our machine bits initialised, work out what
	 * clocks we've got */

	s3c2410_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), 12*MHZ);

	tmp = __raw_readl(S3C2410_CLKDIVN);
	//printk("tmp=%08x, fclk=%d\n", tmp, s3c2410_fclk);

	/* work out clock scalings */

	s3c2410_hclk = s3c2410_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
	s3c2410_pclk = s3c2410_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);

	/* print brieft summary of clocks, etc */

	printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(s3c2410_fclk), print_mhz(s3c2410_hclk),
	       print_mhz(s3c2410_pclk));
}

void __init s3c2410_init_clocks(int xtal)
{
    unsigned long tmp;
    unsigned long fclk;
    unsigned long hclk;
    unsigned long pclk;

    /* now we've got our machine bits initialised, work out what
     * clocks we've got */

    fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);

    tmp = __raw_readl(S3C2410_CLKDIVN);

    /* work out clock scalings */

    hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
    pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);

    /* print brieft summary of clocks, etc */

    printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
           print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

    /* initialise the clocks here, to allow other things like the
     * console to use them
     */

    s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
    s3c2410_baseclk_add();
}

void __init s3c2412_init_clocks(int xtal)
{
	unsigned long clkdiv;
	unsigned long hclk, fclk, pclk;
	int hdiv = 1;

	/* now we've got our machine bits initialised, work out what
	 * clocks we've got */

	fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);

	clkdiv = __raw_readl(S3C2410_CLKDIVN);

	/* work out clock scalings */

	switch (clkdiv & S3C2412_CLKDIVN_HCLKDIV_MASK) {
	case S3C2412_CLKDIVN_HCLKDIV_1_2:
		hdiv = 1;
		break;

	case S3C2412_CLKDIVN_HCLKDIV_2_4:
		hdiv = 2;
		break;

	case S3C2412_CLKDIVN_HCLKDIV_3_6:
		hdiv = 3;
		break;

	case S3C2412_CLKDIVN_HCLKDIV_4_8:
		hdiv = 4;
		break;
	}

	if (!(clkdiv & S3C2412_CLKDIVN_ARMDIV))
		fclk *= 2;

	hclk = fclk / hdiv;
	pclk = hclk / ((clkdiv & S3C2412_CLKDIVN_PCLKDIV)? 2 : 1);
	if (clkdiv & S3C2412_CLKDIVN_DVSEN)
		fclk = hclk;

	/* print brief summary of clocks, etc */

	printk("S3C2412: core %lu.%03lu MHz, memory %lu.%03lu MHz, peripheral %lu.%03lu MHz\n",
		   print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	/* initialise the clocks here, to allow other things like the
	 * console to use them, and to add new ones after the initialisation
	 */

	s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);

#if defined CONFIG_CPU_FREQ && defined CONFIG_S3C24XX_DFS_CPUFREQ
	/* Setup the uartclk. Needs to be done this early so the console can use it. */
	s3c2412_setup_uart_clk( xtal );
#endif
}

void __init s3c244x_init_clocks(int xtal)
{
	unsigned long clkdiv;
	unsigned long camdiv;
	unsigned long hclk, fclk, pclk;
	int hdiv = 1;

	/* now we've got our machine bits initialised, work out what
	 * clocks we've got */

	fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	/* work out clock scalings */

	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	case S3C2440_CLKDIVN_HDIVN_1:
		hdiv = 1;
		break;

	case S3C2440_CLKDIVN_HDIVN_2:
		hdiv = 2;
		break;

	case S3C2440_CLKDIVN_HDIVN_4_8:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
		break;

	case S3C2440_CLKDIVN_HDIVN_3_6:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
		break;
	}

	hclk = fclk / hdiv;
	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);

	/* print brief summary of clocks, etc */

	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	/* initialise the clocks here, to allow other things like the
	 * console to use them, and to add new ones after the initialisation
	 */

	s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
	s3c2410_baseclk_add();
}

void __init_or_cpufreq s3c244x_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long clkdiv;
	unsigned long camdiv;
	unsigned long xtal;
	unsigned long hclk, fclk, pclk;
	int hdiv = 1;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	/* work out clock scalings */

	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	case S3C2440_CLKDIVN_HDIVN_1:
		hdiv = 1;
		break;

	case S3C2440_CLKDIVN_HDIVN_2:
		hdiv = 2;
		break;

	case S3C2440_CLKDIVN_HDIVN_4_8:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
		break;

	case S3C2440_CLKDIVN_HDIVN_3_6:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
		break;
	}

	hclk = fclk / hdiv;
	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);

	/* print brief summary of clocks, etc */

	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

int __init s3c2410_baseclk_add(void)
{
	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
	unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
	struct clk *xtal;
	int ret;
	int ptr;

	clk_upll.enable = s3c2410_upll_enable;

	if (s3c24xx_register_clock(&clk_usb_bus) < 0)
		printk(KERN_ERR "failed to register usb bus clock\n");

	/* register clocks from clock array */

	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
		struct clk *clkp = init_clocks[ptr];

		/* ensure that we note the clock state */

		clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;

		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}

	/* We must be careful disabling the clocks we are not intending to
	 * be using at boot time, as subsystems such as the LCD which do
	 * their own DMA requests to the bus can cause the system to lockup
	 * if they where in the middle of requesting bus access.
	 *
	 * Disabling the LCD clock if the LCD is active is very dangerous,
	 * and therefore the bootloader should be careful to not enable
	 * the LCD clock if it is not needed.
	*/

	/* install (and disable) the clocks we do not need immediately */

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	/* show the clock-slow value */

	xtal = clk_get(NULL, "xtal");

	printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
	       print_mhz(clk_get_rate(xtal) /
			 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
	       (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
	       (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
	       (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");

	s3c_pwmclk_init();
	return 0;
}

void __init_or_cpufreq s5p6440_setup_clocks(void)
{
	struct clk *xtal_clk;

	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk_low;
	unsigned long pclk;
	unsigned long pclk_low;

	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned int ptr;

	/*                                         */

	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5p6440_epll_ops;

	clk_48m.enable = s5p64x0_clk48m_ctrl;

	xtal_clk = clk_get(NULL, "ext_xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
				__raw_readl(S5P64X0_EPLL_CON_K));

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;

	printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
			" E=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll));

	fclk = clk_get_rate(&clk_armclk.clk);
	hclk = clk_get_rate(&clk_hclk.clk);
	pclk = clk_get_rate(&clk_pclk.clk);
	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	pclk_low = clk_get_rate(&clk_pclk_low.clk);

	printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
			" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
			print_mhz(hclk), print_mhz(hclk_low),
			print_mhz(pclk), print_mhz(pclk_low));

	clk_f.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

void __init_or_cpufreq s5pc100_setup_clocks(void)
{
	unsigned long xtal;
	unsigned long arm;
	unsigned long hclkd0;
	unsigned long hclkd1;
	unsigned long pclkd0;
	unsigned long pclkd1;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long hpll;
	unsigned int ptr;

	/* Set S5PC100 functions for clk_fout_epll */
	clk_fout_epll.enable = s5pc100_epll_enable;
	clk_fout_epll.ops = &s5pc100_epll_ops;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal = clk_get_rate(&clk_xtal);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
	mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
	epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
	hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));

	printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_mout_hpll.clk.rate = hpll;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);

	arm = clk_get_rate(&clk_div_arm.clk);
	hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
	pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
	hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
	pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);

	printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
			print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));

	clk_f.rate = arm;
	clk_h.rate = hclkd1;
	clk_p.rate = pclkd1;
}

void
oki_fixup(struct machine_desc *mdesc,
	  struct param_struct *param,
	  char **arg,
	  struct meminfo *meminfo)
{
  unsigned int bwc, tmp;
  unsigned int clk;

  /* need to determine which version of the cpu this is */

  bwc = __raw_readl(OKI_BWC);

  tmp = bwc & ~(3<<8);   /* IO23BW */

  if (tmp != bwc) {
    printk("CPU is ML67400x series\n");

    oki_ml67400x = 1;
    oki_ml67500x = 0;
    oki_clk      = 25*1000*1000;
  } else {
    printk("CPU is ML67500x series\n");

    oki_ml67400x = 0;
    oki_ml67500x = 1;
    oki_clk      = 7372800*8;

    oki_ml67500x_init_cache();
  }

  clk = __raw_readl(OKI_CGBCNT0);

  oki_hclk = oki_clk /  OKI_CLKGR_H(clk);
  oki_cclk = oki_clk /  OKI_CLKGR_C(clk);

#define print_mhz(x) ((x) / 1000000), (((x) / 1000) % 1000)

  printk("OKI: Clk %d.%3d MHz, HClk %d.%3d MHz, CCLk %d.%3d MHz\n",
	 print_mhz(oki_clk), print_mhz(oki_hclk), print_mhz(oki_cclk));

}

int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	bd_t *bd = gd->bd;

	print_bi_mem(bd);
	print_bi_flash(bd);
#if defined(CONFIG_SYS_INIT_RAM_ADDR)
	print_num("sramstart",		(ulong)bd->bi_sramstart);
	print_num("sramsize",		(ulong)bd->bi_sramsize);
#endif
#if defined(CONFIG_SYS_MBAR)
	print_num("mbar",		bd->bi_mbar_base);
#endif
	print_mhz("cpufreq",		bd->bi_intfreq);
	print_mhz("busfreq",		bd->bi_busfreq);
#ifdef CONFIG_PCI
	print_mhz("pcifreq",		bd->bi_pcifreq);
#endif
#ifdef CONFIG_EXTRA_CLOCK
	print_mhz("flbfreq",		bd->bi_flbfreq);
	print_mhz("inpfreq",		bd->bi_inpfreq);
	print_mhz("vcofreq",		bd->bi_vcofreq);
#endif
	print_eth_ip_addr();
	print_baudrate();

	return 0;
}

static int s3c2440_clk_add(struct sys_device *sysdev)
{
    struct clk *clk_xtal;
    struct clk *clk_h;
    struct clk *clk_p;
    int i;
    struct clk *clkp;

    clk_xtal = clk_get(NULL, "xtal");
    if (IS_ERR(clk_xtal)) {
        printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
        return -EINVAL;
    }

    s3c2440_clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), clk_xtal->rate);

    printk("S3C2440: Clock Support, UPLL %lu.%03lu MHz\n",
           print_mhz(s3c2440_clk_upll.rate));

    clk_h = clk_get(NULL, "hclk");
    clk_p = clk_get(NULL, "pclk");

    if (IS_ERR(clk_h) || IS_ERR(clk_p)) {
        printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
        return -EINVAL;
    }

    s3c24xx_register_clock(&s3c2440_clk_upll);

    for (i = 0; i < ARRAY_SIZE(s3c2440_init_clocks); ++i) {
        clkp = &s3c2440_init_clocks[i];
        switch ((int)clkp->parent) {
        case (int)CLK_H:
            clkp->parent = clk_h;
            break;
        case (int)CLK_P:
            clkp->parent = clk_p;
            break;
        default:
            clkp->parent = NULL;
            break;
        }
        s3c24xx_register_clock(clkp);
    }

    return 0;
}