C++ pmic_reg_read函数代码示例

static int s5pc210_phy_control(int on)
{
	int ret = 0;
	u32 val = 0;
	struct pmic *p = get_pmic();

	if (pmic_probe(p))
		return -1;

	if (on) {
		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
				      ENSAFEOUT1, LDO_ON);
		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);

		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
	} else {
		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);

		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
				      ENSAFEOUT1, LDO_OFF);
	}

	if (ret) {
		puts("MAX8997 LDO setting error!\n");
		return -1;
	}

	return 0;
}

int power_init_board(void)
{
	struct pmic *p;
	int ret;
	unsigned int reg, rev_id;

	ret = power_pfuze3000_init(I2C_PMIC);
	if (ret)
		return ret;

	p = pmic_get("PFUZE3000");
	ret = pmic_probe(p);
	if (ret)
		return ret;

	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);

	/* disable Low Power Mode during standby mode */
	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
	reg |= 0x1;
	pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);

	return 0;
}

void power_init(void)
{
	unsigned int val;
	struct pmic *p;

	pmic_init();
	p = get_pmic();

	/* Set VDDA to 1.25V */
	pmic_reg_read(p, REG_SW_2, &val);
	val &= ~SWX_OUT_MASK;
	val |= SWX_OUT_1_25;
	pmic_reg_write(p, REG_SW_2, val);

	/*
	 * Need increase VCC and VDDA to 1.3V
	 * according to MX53 IC TO2 datasheet.
	 */
	if (is_soc_rev(CHIP_REV_2_0) == 0) {
		/* Set VCC to 1.3V for TO2 */
		pmic_reg_read(p, REG_SW_1, &val);
		val &= ~SWX_OUT_MASK;
		val |= SWX_OUT_1_30;
		pmic_reg_write(p, REG_SW_1, val);

		/* Set VDDA to 1.3V for TO2 */
		pmic_reg_read(p, REG_SW_2, &val);
		val &= ~SWX_OUT_MASK;
		val |= SWX_OUT_1_30;
		pmic_reg_write(p, REG_SW_2, val);
	}
}

void ldo_mode_set(int ldo_bypass)
{
	unsigned int value;
	u32 vddarm;

	struct pmic *p = pfuze;

	if (!p) {
		printf("No PMIC found!\n");
		return;
	}

	/* switch to ldo_bypass mode */
	if (ldo_bypass) {
		prep_anatop_bypass();
		/* decrease VDDARM to 1.275V */
		pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
		value &= ~0x1f;
		value |= PFUZE300_SW1AB_SETP(1275);
		pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);

		set_anatop_bypass(1);
		vddarm = PFUZE300_SW1AB_SETP(1175);

		pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
		value &= ~0x1f;
		value |= vddarm;
		pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);

		finish_anatop_bypass();

		printf("switch to ldo_bypass mode!\n");
	}
}

void ldo_mode_set(int ldo_bypass)
{
	unsigned int value;

	struct pmic *p = pfuze;

	if (!p) {
		printf("No PMIC found!\n");
		return;
	}

	/* switch to ldo_bypass mode */
	if (ldo_bypass) {
		/* decrease VDDARM to 1.15V */
		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
		value &= ~0x3f;
		value |= PFUZE100_SW1ABC_SETP(11500);
		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

		/* decrease VDDSOC to 1.15V */
		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
		value &= ~0x3f;
		value |= PFUZE100_SW1ABC_SETP(11500);
		pmic_reg_write(p, PFUZE100_SW1CVOL, value);

		set_anatop_bypass(1);

		printf("switch to ldo_bypass mode!\n");
	}
}

void pmic_88pm886_base_init(struct pmic *p_base)
{
	u32 data;
	/* disable watchdog */
	pmic_update_bits(p_base, 0x1d, (1 << 0), (1 << 0));

	/*----following setting is for Audio Codec ---*/
	/* enable 32Khz low jitter XO_LJ = 1 */
	pmic_update_bits(p_base, 0x21, (1 << 5), (1 << 5));
	/* enable USE_XO = 1 */
	pmic_update_bits(p_base, 0xd0, (1 << 7), (1 << 7));
	/* output 32k from XO */
	pmic_update_bits(p_base, 0xe2, 0xf, 0xa);

	/* read-clear interruption registers */
	pmic_reg_read(p_base, PM886_REG_INT1, &data);
	pmic_reg_read(p_base, PM886_REG_INT2, &data);
	pmic_reg_read(p_base, PM886_REG_INT3, &data);
	pmic_reg_read(p_base, PM886_REG_INT4, &data);

	/*
	 * print out power up/down log and save in memory
	 * the power up log has little change vesus to
	 * 88pm820/88pm860
	 */
	get_powerup_down_log(g_chip);
}

int rtc_get(struct rtc_time *rtc)
{
	u32 day1, day2, time;
	int tim, i = 0;
	struct pmic *p = pmic_get("FSL_PMIC");
	int ret;

	if (!p)
		return -1;
	do {
		ret = pmic_reg_read(p, REG_RTC_DAY, &day1);
		if (ret < 0)
			return -1;

		ret = pmic_reg_read(p, REG_RTC_TIME, &time);
		if (ret < 0)
			return -1;

		ret = pmic_reg_read(p, REG_RTC_DAY, &day2);
		if (ret < 0)
			return -1;

	} while (day1 != day2 && i++ < 3);

	tim = day1 * 86400 + time;

	rtc_to_tm(tim, rtc);

	rtc->tm_yday = 0;
	rtc->tm_isdst = 0;

	return 0;
}

int power_init_board(void)
{
	struct pmic *p;
	unsigned int reg, ret;

	p = pfuze_common_init(I2C_PMIC);
	if (!p)
		return -ENODEV;

	ret = pfuze_mode_init(p, APS_PFM);
	if (ret < 0)
		return ret;

	/* Increase VGEN3 from 2.5 to 2.8V */
	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
	reg &= ~LDO_VOL_MASK;
	reg |= LDOB_2_80V;
	pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);

	/* Increase VGEN5 from 2.8 to 3V */
	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
	reg &= ~LDO_VOL_MASK;
	reg |= LDOB_3_00V;
	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);

	return 0;
}

static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
{
	int val;
	struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
	struct pfuze100_regulator_desc *desc = plat->desc;

	if (op == PMIC_OP_GET) {
		if (desc->type == REGULATOR_TYPE_BUCK) {
			if (!strcmp(dev->name, "swbst")) {
				val = pmic_reg_read(dev->parent,
						    desc->vsel_reg);
				if (val < 0)
					return val;

				val &= SWBST_MODE_MASK;
				val >>= SWBST_MODE_SHIFT;
				*opmode = val;

				return 0;
			}
			val = pmic_reg_read(dev->parent,
					    desc->vsel_reg +
					    PFUZE100_MODE_OFFSET);
			if (val < 0)
				return val;

			val &= SW_MODE_MASK;
			val >>= SW_MODE_SHIFT;
			*opmode = val;

			return 0;

		} else if (desc->type == REGULATOR_TYPE_LDO) {

/* setup board specific PMIC */
int power_init_board(void)
{
	struct pmic *p;
	u32 reg;
	int ret;

	power_pfuze100_init(1);
	p = pmic_get("PFUZE100");
	if (!p)
		return -EINVAL;

	ret = pmic_probe(p);
	if (ret)
		return ret;

	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);

	/* Set SWBST to 5.0V and enable (for USB) */
	pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
	reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
	reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
	pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);

	return 0;
}

void pmic_88pm880_base_init(struct pmic *p_base)
{
	u32 data;
	/* disable watchdog */
	pmic_update_bits(p_base, PM880_REG_WDOG, PM880_REG_WDOG_DIS, PM880_REG_WDOG_DIS);

	/*----following setting is for Audio Codec ---*/
	/* enable 32Khz low jitter XO_LJ = 1 */
	pmic_update_bits(p_base, PM880_REG_LOWPOWER2, PM880_REG_XO_LJ, PM880_REG_XO_LJ);
	/* enable USE_XO = 1 */
	pmic_update_bits(p_base, PM880_REG_RTC_CTRL1, PM880_REG_USE_XO, PM880_REG_USE_XO);
	/* output 32k from XO */
	pmic_update_bits(p_base, PM880_REG_AON_CTRL2, PM880_CLK32K2_SEL_MASK, PM880_CLK32K2_SEL_32);

	/* read-clear interruption registers */
	pmic_reg_read(p_base, PM880_REG_INT1, &data);
	pmic_reg_read(p_base, PM880_REG_INT2, &data);
	pmic_reg_read(p_base, PM880_REG_INT3, &data);
	pmic_reg_read(p_base, PM880_REG_INT4, &data);

	/* turn on cfd clock, so we could turn off CFD_PLS_EN later */
	pmic_update_bits(p_base, PM880_REG_CLK_CTRL_1, PM880_CFD_CLK_EN, PM880_CFD_CLK_EN);

	/*
	 * print out power up/down log and save in memory
	 * the power up log has little change vesus to
	 * 88pm820/88pm860/88pm880
	 */
	get_powerup_down_log(g_chip);
}

void exynos_lcd_power_on(void)
{
	struct udevice *dev;
	int ret;
	u8 reg;

	ret = pmic_get("max8998-pmic", &dev);
	if (ret) {
		puts("Failed to get MAX8998!\n");
		return;
	}

	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
	reg |= MAX8998_LDO17;
	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
	if (ret) {
		puts("MAX8998 LDO setting error\n");
		return;
	}

	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
	reg |= MAX8998_LDO7;
	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
	if (ret) {
		puts("MAX8998 LDO setting error\n");
		return;
	}
}

static int pmic_clk_enable(struct clk_hw *hw)
{
	struct pmic_clk *clk_pmic = container_of(hw, struct pmic_clk, hw);
    u32    reg_val = 0;
    unsigned long rfclk_flag = 0;

    spin_lock_irqsave(&g_pmic_xoinfo.xorf_lock, rfclk_flag);
    /* 打开前写0 */
    pmic_reg_read(clk_pmic->freq_addr_offset, &reg_val);
    reg_val &= (~(clk_pmic->freq_mask));
    pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);

    /*enable clk*/
    pmic_mutli_core_lock();

    pmic_reg_read(clk_pmic->en_dis_offset, &reg_val);
    reg_val |= (((u32)0x1) << clk_pmic->en_dis_bit);
    pmic_reg_write(clk_pmic->en_dis_offset, reg_val);

    pmic_mutli_core_unlock();
    /*delay 6us*/
    udelay(clk_pmic->delay_us);

    /* 打开后写1 */
    pmic_reg_read(clk_pmic->freq_addr_offset, &reg_val);
    reg_val |= clk_pmic->freq_mask;
    pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);

    spin_unlock_irqrestore(&g_pmic_xoinfo.xorf_lock, rfclk_flag);

    return 0;
}

static int power_init(void)
{
	unsigned int val;
	int ret = -1;
	struct pmic *p;

	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
		pmic_dialog_init();
		p = get_pmic();

		/* Set VDDA to 1.25V */
		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);

		ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
		val |= DA9052_SUPPLY_VBCOREGO;
		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);

		/* Set Vcc peripheral to 1.30V */
		ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
	}

	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
		pmic_init();
		p = get_pmic();

		/* Set VDDGP to 1.25V for 1GHz on SW1 */
		pmic_reg_read(p, REG_SW_0, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
		ret = pmic_reg_write(p, REG_SW_0, val);

		/* Set VCC as 1.30V on SW2 */
		pmic_reg_read(p, REG_SW_1, &val);
		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
		ret |= pmic_reg_write(p, REG_SW_1, val);

		/* Set global reset timer to 4s */
		pmic_reg_read(p, REG_POWER_CTL2, &val);
		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
		ret |= pmic_reg_write(p, REG_POWER_CTL2, val);

		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
		pmic_reg_read(p, REG_MODE_0, &val);
		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
		ret |= pmic_reg_write(p, REG_MODE_0, val);

		/* Set SWBST to 5V in auto mode */
		val = SWBST_AUTO;
		ret |= pmic_reg_write(p, SWBST_CTRL, val);
	}

	return ret;
}

void board_pmic_power_fixup(struct pmic *p_power)
{
	u32 val;
	/* Set VCC_main(buck1) as 1.2v*/
	val = 0x30;
	pmic_reg_write(p_power, 0x3c, val);
	pmic_reg_write(p_power, 0x3d, val);
	pmic_reg_write(p_power, 0x3e, val);
	pmic_reg_write(p_power, 0x3f, val);

	/* Set buck4 as 1.8V */
	val = 0x54;
	pmic_reg_write(p_power, 0x42, val);
	pmic_reg_write(p_power, 0x43, val);
	pmic_reg_write(p_power, 0x44, val);
	pmic_reg_write(p_power, 0x45, val);


	/* Set buck1 ramp up speed to 12.5mV/us */
	pmic_reg_read(p_power, 0x78, &val);
	val &= ~(7 << 3);
	val |= (0x6 << 3);
	pmic_reg_write(p_power, 0x78, val);

	/* Set buck1 audio mode as 0.8V */
	val = 0x10;
	pmic_reg_write(p_power, 0x38, val);

	/* enable buck1 sleep modewhen SLEEpn = '0' */
	pmic_reg_read(p_power, 0x5a, &val);
	val &= 0xfc;
	val |= 0x2;
	pmic_reg_write(p_power, 0x5a, val);

	/* Set LDO8 as 3.1V for LCD  */
	marvell88pm_set_ldo_vol(p_power, 8, 3100000);

	/* Set LDO12 as 3.0V for SD IO/bus */
	marvell88pm_set_ldo_vol(p_power, 12, 3000000);

	/* Set LDO13 as 3.0V for SD Card */
	marvell88pm_set_ldo_vol(p_power, 13, 3000000);

	/* Set LDO14 as 3.0V for eMMC */
	marvell88pm_set_ldo_vol(p_power, 14, 3000000);

	/* Set LDO15 as 1.8V for LCD  */
	marvell88pm_set_ldo_vol(p_power, 15, 1800000);

	/* Set vbuck1 sleep voltage is 0.8V */
	val = 0x10;
	pmic_reg_write(p_power, 0x30, val);
}