本文整理汇总了C++中phy_write函数的典型用法代码示例。如果您正苦于以下问题:C++ phy_write函数的具体用法?C++ phy_write怎么用?C++ phy_write使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了phy_write函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: marvell_config_aneg
static int marvell_config_aneg(struct phy_device *phydev)
{
int err;
/*
*/
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
if (err < 0)
return err;
err = phy_write(phydev, 0x1d, 0x1f);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0x200c);
if (err < 0)
return err;
err = phy_write(phydev, 0x1d, 0x5);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0);
if (err < 0)
return err;
err = phy_write(phydev, 0x1e, 0x100);
if (err < 0)
return err;
err = phy_write(phydev, MII_M1011_PHY_SCR,
MII_M1011_PHY_SCR_AUTO_CROSS);
if (err < 0)
return err;
err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
MII_M1111_PHY_LED_DIRECT);
if (err < 0)
return err;
err = genphy_config_aneg(phydev);
if (err < 0)
return err;
if (phydev->autoneg != AUTONEG_ENABLE) {
int bmcr;
/*
*/
bmcr = phy_read(phydev, MII_BMCR);
if (bmcr < 0)
return bmcr;
err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
if (err < 0)
return err;
}
return 0;
}
示例2: cs4340_upload_firmware
void cs4340_upload_firmware(struct phy_device *phydev)
{
char line_temp[0x50] = {0};
char reg_addr[0x50] = {0};
char reg_data[0x50] = {0};
int i, line_cnt = 0, column_cnt = 0;
struct cortina_reg_config fw_temp;
char *addr = NULL;
#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
addr = (char *)CONFIG_CORTINA_FW_ADDR;
#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
int ret;
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_CORTINA_FW_ADDR,
&fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
CONFIG_CORTINA_FW_ADDR, ret);
}
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
int ret;
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
CONFIG_CORTINA_FW_LENGTH, addr);
if (ret)
puts("SF: read for Cortina ucode failed\n");
spi_flash_free(ucode_flash);
}
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
puts("Failed to find MMC device for Cortina ucode\n");
} else {
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
}
#endif
while (*addr != 'Q') {
i = 0;
while (*addr != 0x0a) {
line_temp[i++] = *addr++;
if (0x50 < i) {
printf("Not found Cortina PHY ucode at 0x%p\n",
(char *)CONFIG_CORTINA_FW_ADDR);
return;
}
}
addr++; /* skip '\n' */
line_cnt++;
column_cnt = i;
line_temp[column_cnt] = '\0';
if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
return;
for (i = 0; i < column_cnt; i++) {
if (isspace(line_temp[i++]))
break;
}
memcpy(reg_addr, line_temp, i);
memcpy(reg_data, &line_temp[i], column_cnt - i);
strim(reg_addr);
strim(reg_data);
fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
0xffff;
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
}
}
示例3: dp83867_config_init
static int dp83867_config_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867;
int ret, val, bs;
u16 delay;
if (!phydev->priv) {
dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
GFP_KERNEL);
if (!dp83867)
return -ENOMEM;
phydev->priv = dp83867;
ret = dp83867_of_init(phydev);
if (ret)
return ret;
} else {
dp83867 = (struct dp83867_private *)phydev->priv;
}
/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
if (dp83867->rxctrl_strap_quirk) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
val &= ~BIT(7);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
}
if (phy_interface_is_rgmii(phydev)) {
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)
return val;
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
/* The code below checks if "port mirroring" N/A MODE4 has been
* enabled during power on bootstrap.
*
* Such N/A mode enabled by mistake can put PHY IC in some
* internal testing mode and disable RGMII transmission.
*
* In this particular case one needs to check STRAP_STS1
* register's bit 11 (marked as RESERVED).
*/
bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
if (bs & DP83867_STRAP_STS1_RESERVED)
val &= ~DP83867_PHYCR_RESERVED_MASK;
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
}
if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
val |= DP83867_RGMII_TX_CLK_DELAY_EN;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
val |= DP83867_RGMII_RX_CLK_DELAY_EN;
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
delay = (dp83867->rx_id_delay |
(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
delay);
if (dp83867->io_impedance >= 0) {
val = phy_read_mmd(phydev, DP83867_DEVADDR,
DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
val |= dp83867->io_impedance &
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
phy_write_mmd(phydev, DP83867_DEVADDR,
DP83867_IO_MUX_CFG, val);
}
}
/* Enable Interrupt output INT_OE in CFG3 register */
if (phy_interrupt_is_valid(phydev)) {
val = phy_read(phydev, DP83867_CFG3);
val |= BIT(7);
phy_write(phydev, DP83867_CFG3, val);
}
if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
dp83867_config_port_mirroring(phydev);
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
//.........这里部分代码省略.........
示例4: m88e1318_set_wol
static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
{
int err, oldpage, temp;
oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
if (wol->wolopts & WAKE_MAGIC) {
/* Explicitly switch to page 0x00, just to be sure */
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
if (err < 0)
return err;
/* Enable the WOL interrupt */
temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
if (err < 0)
return err;
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
MII_88E1318S_PHY_LED_PAGE);
if (err < 0)
return err;
/* Setup LED[2] as interrupt pin (active low) */
temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
if (err < 0)
return err;
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
MII_88E1318S_PHY_WOL_PAGE);
if (err < 0)
return err;
/* Store the device address for the magic packet */
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
((phydev->attached_dev->dev_addr[5] << 8) |
phydev->attached_dev->dev_addr[4]));
if (err < 0)
return err;
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
((phydev->attached_dev->dev_addr[3] << 8) |
phydev->attached_dev->dev_addr[2]));
if (err < 0)
return err;
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
((phydev->attached_dev->dev_addr[1] << 8) |
phydev->attached_dev->dev_addr[0]));
if (err < 0)
return err;
/* Clear WOL status and enable magic packet matching */
temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
if (err < 0)
return err;
} else {
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
MII_88E1318S_PHY_WOL_PAGE);
if (err < 0)
return err;
/* Clear WOL status and disable magic packet matching */
temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
if (err < 0)
return err;
}
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
if (err < 0)
return err;
return 0;
}
示例5: m88e1111_config_init
static int m88e1111_config_init(struct phy_device *phydev)
{
int err;
int temp;
if (phy_interface_is_rgmii(phydev)) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
if (temp < 0)
return temp;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
temp &= ~MII_M1111_TX_DELAY;
temp |= MII_M1111_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
temp &= ~MII_M1111_RX_DELAY;
temp |= MII_M1111_TX_DELAY;
}
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
if (err < 0)
return err;
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
else
temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
/* make sure copper is selected */
err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
if (err < 0)
return err;
err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
err & (~0xff));
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
if (temp < 0)
return temp;
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
if (err < 0)
return err;
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
/* soft reset */
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
if (err < 0)
return err;
do
temp = phy_read(phydev, MII_BMCR);
while (temp & BMCR_RESET);
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
}
//.........这里部分代码省略.........
示例6: edm_cf_imx6_fec_phy_init
static int edm_cf_imx6_fec_phy_init(struct phy_device *phydev)
{
unsigned short val;
/* Ar8031 phy SmartEEE feature cause link status generates glitch,
* which cause ethernet link down/up issue, so disable SmartEEE
*/
phy_write(phydev, 0xd, 0x3);
phy_write(phydev, 0xe, 0x805d);
phy_write(phydev, 0xd, 0x4003);
val = phy_read(phydev, 0xe);
val &= ~(0x1 << 8);
phy_write(phydev, 0xe, val);
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, 0xd, 0x7);
phy_write(phydev, 0xe, 0x8016);
phy_write(phydev, 0xd, 0x4007);
val = phy_read(phydev, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, 0xe, val);
/* Introduce tx clock delay */
phy_write(phydev, 0x1d, 0x5);
val = phy_read(phydev, 0x1e);
val |= 0x0100;
phy_write(phydev, 0x1e, val);
/*check phy power*/
val = phy_read(phydev, 0x0);
if (val & BMCR_PDOWN)
phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
return 0;
}
示例7: ksz9021_phy_extended_read
int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
{
/* extended registers */
phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}
示例8: ethernet_init
/*----------------------------------------------------------------------------
Ethernet Device initialize
*----------------------------------------------------------------------------*/
int ethernet_init() {
int regv, tout;
char mac[ETHERNET_ADDR_SIZE];
unsigned int clock = clockselect();
LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
for(tout = 100; tout; tout--) __NOP(); /* A short delay */
LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
LPC_EMAC->MCMD = 0;
LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
for (tout = 100; tout; tout--) __NOP(); /* A short delay */
LPC_EMAC->SUPP = 0;
phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
regv = phy_read(PHY_REG_BMCR);
if(regv < 0 || tout == 0) {
return -1; /* Error */
}
if(!(regv & PHY_BMCR_RESET)) {
break; /* Reset complete. */
}
}
ethernet_set_link(-1, 0);
/* Set the Ethernet MAC Address registers */
ethernet_address(mac);
LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
txdscr_init(); /* initialize DMA TX Descriptor */
rxdscr_init(); /* initialize DMA RX Descriptor */
LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
/* Receive Broadcast, Perfect Match Packets */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->MAC1 |= MAC1_REC_EN;
#if NEW_LOGIC
rx_consume_offset = -1;
tx_produce_offset = -1;
#else
send_doff = 0;
send_idx = -1;
send_size = 0;
receive_soff = 0;
receive_idx = -1;
#endif
return 0;
}
示例9: bcm54xx_shadow_read
/*
* Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
* 0x1c shadow registers.
*/
static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
{
phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
}
示例10: ksz8021_config_init
static int ksz8021_config_init(struct phy_device *phydev)
{
const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
phy_write(phydev, MII_KSZPHY_OMSO, val);
return 0;
}
示例11: ksz8091_set_wol
static int ksz8091_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
{
int err, oldpage, temp;
int i = 0;
oldpage = phy_read(phydev, KSZ8091_MMD_CTRL);
/*
Magic-packet detection is enabled by writing a 1 to MMD address 1Fh,register 0h, bit [6]
The MAC address (for the local MAC device) is written to and stored in MMD address 1Fh, registers 19h -1Bh
The KSZ8091MNX/RNB does not generate the magic packet. The magic packet must be provided by the external system.
*/
printk("wol->wolopts = %d\nWAKE_MAGIC = %d\n",wol->wolopts,WAKE_MAGIC);
if (wol->wolopts & WAKE_MAGIC) {
temp = phy_read(phydev, KSZ8091_WOL_OMSO);
phy_write(phydev, KSZ8091_WOL_OMSO,temp| 1<<15);
/* Explicitly switch to page 0x1F, just to be sure */
printk("wol->wolopts = %d\nWAKE_MAGIC = %d\n",wol->wolopts,WAKE_MAGIC);
for(i =0;i< 6;i++){
printk("phydev->attached_dev->dev_addr[%d] = %x \n ",i,phydev->attached_dev->dev_addr[i]);
}
/* Store the device address for the magic packet */
/***************************************KSZ8091_WOL_MACDA2************************************************************/
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA2);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[5] ) << 8 |(phydev->attached_dev->dev_addr[4]));
if (err < 0)
return err;
/***************************************KSZ8091_WOL_MACDA1*********************************************/
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA1);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[3] ) << 8 | (phydev->attached_dev->dev_addr[2]));
if (err < 0)
return err;
/***************************************KSZ8091_WOL_MACDA0*****************************************************/
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_MACDA0);// select reg 0
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, (phydev->attached_dev->dev_addr[1] ) << 8 |(phydev->attached_dev->dev_addr[0]));
if (err < 0)
return err;
/**************************************************MACEND***************************************************/
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_C);// select reg 0
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, 1<<6| 1<<14); //link down enable
if (err < 0)
return err;
/* Clear WOL status and enable magic packet matching */
} else {
// write addr 1f reg 0 bit6 0 disable Magic
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x1F);
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, KSZ8091_WOL_C);// select reg 0
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_CTRL, 0x401f); //write
if (err < 0)
return err;
err = phy_write(phydev, KSZ8091_MMD_REG_DATA, ~(1<<6)); //link down enable
if (err < 0)
return err;
temp = phy_read(phydev, KSZ8091_WOL_OMSO);
phy_write(phydev, KSZ8091_WOL_OMSO,temp|~( 1<<15));
}
return 0;
}
示例12: ksz9031_RNX_config_init
static int ksz9031_RNX_config_init(struct phy_device *phydev)
{/*Set Auto-Negotiation FLP interval to 16ms using the following programming sequence to set MMD ? Device Address 0h, Register 4h = 0x0006
and MMD ? Device Address 0h, Register 3h = 0x1A80
*/
int val=0;
cnt = 0;
#if 1
phy_write(phydev,MMD_CTRL,0x0);
phy_write(phydev,MMD_REG_DATA,0x4);
phy_write(phydev,MMD_CTRL,0x4000);
phy_write(phydev,MMD_REG_DATA,0x6);
phy_write(phydev,MMD_CTRL,0x0);
phy_write(phydev,MMD_REG_DATA,0x3);
phy_write(phydev,MMD_CTRL,0x4000);
phy_write(phydev,MMD_REG_DATA,0x1A80);
phy_write(phydev,MMD_CTRL,0x1);
phy_write(phydev,MMD_REG_DATA,0x5a);
phy_write(phydev,MMD_CTRL,0x4001);
phy_write(phydev,MMD_REG_DATA,0x106);
#endif
printk("----micrel phy init--------\n");
/*
delay rxclock
SET MMD ? Device Address 2h, Register 8h = 0x01F
*/
#if 0
phy_write(phydev,MMD_CTRL,0x2);
phy_write(phydev,MMD_REG_DATA,0x8);
phy_write(phydev,MMD_CTRL,0x4002);
phy_write(phydev,MMD_REG_DATA,0x3de0);
#endif
phy_write(phydev,MMD_CTRL,0x2);
phy_write(phydev,MMD_REG_DATA,0x5);
phy_write(phydev,MMD_CTRL,0x4002);
phy_write(phydev,MMD_REG_DATA,0xffff);
phy_write(phydev,0x4,0x5e1);
val=phy_read(phydev,0x0);
phy_write(phydev,0x0,val| 1<<9);
return 0;
}
示例13: m88e1111_config_init
static int m88e1111_config_init(struct phy_device *phydev)
{
int err;
int temp;
/* */
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
temp = phy_read(phydev, MII_BMCR);
temp |= BMCR_RESET;
phy_write(phydev, MII_BMCR, temp);
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
if (temp < 0)
return temp;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
temp &= ~MII_M1111_TX_DELAY;
temp |= MII_M1111_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
temp &= ~MII_M1111_RX_DELAY;
temp |= MII_M1111_TX_DELAY;
}
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
if (err < 0)
return err;
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
else
temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
}
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
if (temp < 0)
return temp;
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
if (err < 0)
return err;
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
return err;
/* */
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
if (err < 0)
return err;
do
temp = phy_read(phydev, MII_BMCR);
while (temp & BMCR_RESET);
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
if (temp < 0)
return temp;
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
if (err < 0)
//.........这里部分代码省略.........
示例14: rtl8211e_config_init
static int rtl8211e_config_init(struct phy_device *phydev)
{
int val;
/* Disable CLK_OUT */
phy_write(phydev, RTL8211F_REGPAGE, 0x0a43); // return to page 0xa43
val = phy_read(phydev, RTL8211F_PHYCR2);
phy_write(phydev, RTL8211F_PHYCR2, val & ~(1 << 0));// disable clock out
phy_write(phydev, RTL8211F_REGPAGE, 0x0000); // return to page 0
phy_write(phydev, RTL8211F_REGPAGE, 0x0a43); // return to page 0xa43
#ifdef RTL_SPRD_CLK_MODE
phy_write(phydev, 0x19, 0x8eb); // 125mhz clock, rxc ssc, clock ssc, and enable EEE
#else
phy_write(phydev, 0x19, 0x803); // 125mhz clock, no EEE, RXC clock enable, clock
#endif
#ifdef RTL_GREEN_MODE
phy_write(phydev, RTL8211F_REGPAGE, 0x0000); // return to page 0
phy_write(phydev, 31, 0x0a43); /* 3, hk test values */
phy_write(phydev, 27, 0x8011); // I do it twice since not sure yet if it survives PHY reset
phy_write(phydev, 28, 0x573f); // boosted perf about 2-3%
#endif
printk("am_rtl811f called phy reset\n");
phy_write(phydev, RTL8211F_PHYCTRL, 0x9200); // PHY reset
msleep(10); // calls for min 50msec
#ifdef RTL_GREEN_MODE
phy_write(phydev, 31, 0x0a43); /* 3, hk test values */
phy_write(phydev, 27, 0x8011);
phy_write(phydev, 28, 0x573f);
#endif
// can modify the last write, 0x00 disables EEE
phy_write(phydev, RTL8211F_MMD_CTRL, 0x7); // device 7
phy_write(phydev, RTL8211F_MMD_DATA, 0x3c); // address 0x3c
phy_write(phydev, RTL8211F_MMD_CTRL, 0x4007); // no post increment, reg 7 again
phy_write(phydev, RTL8211F_MMD_DATA, 0x00);
return 0;
}
示例15: dp83867_config_init
static int dp83867_config_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867;
int ret, bs;
u16 val, delay, cfg2;
if (!phydev->priv) {
dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
GFP_KERNEL);
if (!dp83867)
return -ENOMEM;
phydev->priv = dp83867;
ret = dp83867_of_init(phydev);
if (ret)
return ret;
} else {
dp83867 = (struct dp83867_private *)phydev->priv;
}
/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
if (dp83867->rxctrl_strap_quirk) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
val &= ~BIT(7);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
}
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
return ret;
val = phy_read(phydev, MII_DP83867_PHYCTRL);
if (val < 0)
return val;
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
/* The code below checks if "port mirroring" N/A MODE4 has been
* enabled during power on bootstrap.
*
* Such N/A mode enabled by mistake can put PHY IC in some
* internal testing mode and disable RGMII transmission.
*
* In this particular case one needs to check STRAP_STS1
* register's bit 11 (marked as RESERVED).
*/
bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
if (bs & DP83867_STRAP_STS1_RESERVED)
val &= ~DP83867_PHYCR_RESERVED_MASK;
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
} else {
/* Set SGMIICTL1 6-wire mode */
if (dp83867->wiremode_6)
phy_write_mmd(phydev, DP83867_DEVADDR,
DP83867_SGMIITYPE, DP83867_SGMIICLK_EN);
phy_write(phydev, MII_BMCR,
(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
cfg2 = phy_read(phydev, MII_DP83867_CFG2);
cfg2 &= MII_DP83867_CFG2_MASK;
cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
MII_DP83867_CFG2_SGMII_AUTONEGEN |
MII_DP83867_CFG2_SPEEDOPT_ENH |
MII_DP83867_CFG2_SPEEDOPT_CNT |
MII_DP83867_CFG2_SPEEDOPT_INTLOW);
phy_write(phydev, MII_DP83867_CFG2, cfg2);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, 0x0);
phy_write(phydev, MII_DP83867_PHYCTRL,
DP83867_PHYCTRL_SGMIIEN |
(DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER) |
(dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
(dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
phy_write(phydev, MII_DP83867_BISCR, 0x0);
/* This is a SW workaround for link instability if
* RX_CTRL is not strapped to mode 3 or 4 in HW.
*/
if (dp83867->rxctrl_strap_quirk) {
val = phy_read_mmd(phydev, DP83867_DEVADDR,
DP83867_CFG4);
val &= ~DP83867_CFG4_RESVDBIT7;
val |= DP83867_CFG4_RESVDBIT8;
val &= ~DP83867_CFG4_SGMII_AUTONEG_TIMER_MASK;
val |= DP83867_CFG4_SGMII_AUTONEG_TIMER_11MS;
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
val);
}
}
//.........这里部分代码省略.........