C++ pci_write_config_word函数代码示例

/*
 * Store the basic register settings needed by the controller.
 */
static void configure_hc(struct uhci_hcd *uhci)
{
	/* Set the frame length to the default: 1 ms exactly */
	outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);

	/* Store the frame list base address */
	outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);

	/* Set the current frame number */
	outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER,
			uhci->io_addr + USBFRNUM);

	/* Mark controller as not halted before we enable interrupts */
	uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
	mb();

	/* Enable PIRQ */
	pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
			USBLEGSUP_DEFAULT);
}

static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
{
	static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int dn = 2 * ap->port_no + adev->devno;
	int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
	u32 pio_timing_data;
	u16 pio_mode_data;

	pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x7 << (4 * dn));
	pio_mode_data |= pio << (4 * dn);
	pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xFF << timing_shift);
	pio_timing_data |= (pio_timings[pio] << timing_shift);
	pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
}

unsigned long
_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
{
    unsigned long   rval;
    unsigned short  pcistat;
    int             count;

    if (enableMCP)
        return -1; /* exceptions not supported / MCP not wired */

    /* read error status for info return */
    pci_read_config_word(0,0,0,PCI_STATUS,&pcistat);
    rval = pcistat;

    count=10;
    do {
        /* clear error reporting registers */

        /* clear PCI status register */
        pci_write_config_word(0,0,0,PCI_STATUS, PCI_ERR_BITS);

        /* read  new status */
        pci_read_config_word(0,0,0,PCI_STATUS, &pcistat);

    } while ( ! PCI_STATUS_OK(pcistat) && count-- );

    if ( !PCI_STATUS_OK(rval) && !quiet) {
        printk("Cleared PCI errors: pci_stat was 0x%04x\n", rval);
    }
    if ( !PCI_STATUS_OK(pcistat) ) {
        printk("Unable to clear PCI errors: still 0x%04x after 10 attempts\n", pcistat);
    }

    rval &= PCI_ERR_BITS;

    /* Some VME bridges (Tsi148) don't propagate VME bus errors to PCI status reg. */
    if ( _BSP_clear_vmebridge_errors )
        rval |= _BSP_clear_vmebridge_errors(quiet)<<16;

    return rval;
}

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	int rc;
	u16 ctrl;

	BUG_ON(dev->ats && dev->ats->is_enabled);

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	if (dev->is_physfn || dev->is_virtfn) {
		struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;

		mutex_lock(&pdev->sriov->lock);
		if (pdev->ats)
			rc = pdev->ats->stu == ps ? 0 : -EINVAL;
		else
			rc = ats_alloc_one(pdev, ps);

		if (!rc)
			pdev->ats->ref_cnt++;
		mutex_unlock(&pdev->sriov->lock);
		if (rc)
			return rc;
	}

	if (!dev->is_physfn) {
		rc = ats_alloc_one(dev, ps);
		if (rc)
			return rc;
	}

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);

	dev->ats->is_enabled = 1;

	return 0;
}

static inline int
pcibios_enable_resources (struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;

	if (!dev)
		return -EINVAL;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
		/* Only set up the desired resources.  */
		if (!(mask & (1 << idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & type_mask))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR
			       "PCI: Device %s not available because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
{
	int err;

	if (!atomic_read(&dev->enable_cnt) && is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG "pciback: %s: enable\n",
			       pci_name(dev));
		err = pci_enable_device(dev);
		if (err)
			return err;
	} else if (atomic_read(&dev->enable_cnt) && !is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG "pciback: %s: disable\n",
			       pci_name(dev));
		pci_disable_device(dev);
	}

	if (!dev->is_busmaster && is_master_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG "pciback: %s: set bus master\n",
			       pci_name(dev));
		pci_set_master(dev);
	}

	if (value & PCI_COMMAND_INVALIDATE) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG
			       "pciback: %s: enable memory-write-invalidate\n",
			       pci_name(dev));
		err = pci_set_mwi(dev);
		if (err) {
			printk(KERN_WARNING
			       "pciback: %s: cannot enable memory-write-invalidate (%d)\n",
			       pci_name(dev), err);
			value &= ~PCI_COMMAND_INVALIDATE;
		}
	}

	return pci_write_config_word(dev, offset, value);
}

void
FreeDriverData( struct EMU10kxData* dd,
		struct DriverBase*  AHIsubBase )
{
  if( dd != NULL )
  {
    if( dd->card.pci_dev != NULL )
    {
      if( dd->emu10k1_initialized )
      {
        emu10k1_cleanup( &dd->card );
      }

      if( dd->pci_master_enabled )
      {
        UWORD cmd;

        #ifdef __AMIGAOS4__
        cmd = ((struct PCIDevice * ) dd->card.pci_dev)->ReadConfigWord( PCI_COMMAND );
        cmd &= ~( PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER );
        ((struct PCIDevice * ) dd->card.pci_dev)->WriteConfigWord( PCI_COMMAND, cmd );
        #else
        cmd = pci_read_config_word( PCI_COMMAND, dd->card.pci_dev );
        cmd &= ~( PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER );
        pci_write_config_word( PCI_COMMAND, cmd, dd->card.pci_dev );
        #endif
      }
    }

    if( dd->interrupt_added )
    {
      #ifdef __AMIGAOS4__
      RemIntServer(((struct PCIDevice * ) dd->card.pci_dev)->MapInterrupt(), &dd->interrupt );
      #else
      pci_rem_intserver( &dd->interrupt, dd->card.pci_dev );
      #endif
    }

    FreeVec( dd );
  }
}

/*
 * Make sure the controller is completely inactive, unable to
 * generate interrupts or do DMA.
 */
static void reset_hc(struct uhci_hcd *uhci)
{
    int port;

    /* Turn off PIRQ enable and SMI enable.  (This also turns off the
     * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
     */
    pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
                          USBLEGSUP_RWC);

    /* Reset the HC - this will force us to get a
     * new notification of any already connected
     * ports due to the virtual disconnect that it
     * implies.
     */
    outw(USBCMD_HCRESET, uhci->io_addr + USBCMD);
    mb();
    udelay(5);
    if (inw(uhci->io_addr + USBCMD) & USBCMD_HCRESET)
        dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n");

    /* Just to be safe, disable interrupt requests and
     * make sure the controller is stopped.
     */
    outw(0, uhci->io_addr + USBINTR);
    outw(0, uhci->io_addr + USBCMD);

    /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
     * bits in the port status and control registers.
     * We have to clear them by hand.
     */
    for (port = 0; port < uhci->rh_numports; ++port)
        outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));

    uhci->port_c_suspend = uhci->suspended_ports =
                               uhci->resuming_ports = 0;
    uhci->rh_state = UHCI_RH_RESET;
    uhci->is_stopped = UHCI_IS_STOPPED;
    uhci_to_hcd(uhci)->state = HC_STATE_HALT;
    uhci_to_hcd(uhci)->poll_rh = 0;
}

static void aer_error_resume(struct pci_dev *dev)
{
	int pos;
	u32 status, mask;
	u16 reg16;

	
	pos = pci_pcie_cap(dev);
	pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16);
	pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);

	
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
	if (dev->error_state == pci_channel_io_normal)
		status &= ~mask; 
	else
		status &= mask; 
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
}

static void __devexit ichxrom_remove_one (struct pci_dev *pdev)
{
	struct ichxrom_map_info *info = &ichxrom_map;
	u16 word;

	del_mtd_device(info->mtd);
	map_destroy(info->mtd);
	info->mtd = NULL;
	info->map.map_priv_1 = 0;

	iounmap((void *)(info->window_addr));
	info->window_addr = 0;

	/* Disable writes through the rom window */
	pci_read_config_word(pdev, BIOS_CNTL, &word);
	pci_write_config_word(pdev, BIOS_CNTL, word & ~1);

#if RESERVE_MEM_REGION	
	release_mem_region(ICHX_FWH_REGION_START, ICHX_FWH_REGION_SIZE);
#endif
}

/**
 * aer_error_resume - clean up corresponding error status bits
 * @dev: pointer to Root Port's pci_dev data structure
 *
 * Invoked by Port Bus driver during nonfatal recovery.
 **/
static void aer_error_resume(struct pci_dev *dev)
{
	int pos;
	u32 status, mask;
	u16 reg16;

	/* Clean up Root device status */
	pos = pci_pcie_cap(dev);
	pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16);
	pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);

	/* Clean AER Root Error Status */
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
	if (dev->error_state == pci_channel_io_normal)
		status &= ~mask; /* Clear corresponding nonfatal bits */
	else
		status &= mask; /* Clear corresponding fatal bits */
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
}

int pci_disable_pcie_error_reporting(struct pci_dev *dev)
{
	u16 reg16 = 0;
	int pos;

	if (pcie_aer_get_firmware_first(dev))
		return -EIO;

	pos = pci_pcie_cap(dev);
	if (!pos)
		return -EIO;

	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
	reg16 &= ~(PCI_EXP_DEVCTL_CERE |
		PCI_EXP_DEVCTL_NFERE |
		PCI_EXP_DEVCTL_FERE |
		PCI_EXP_DEVCTL_URRE);
	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);

	return 0;
}

static void radisys_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
    unsigned int pio	= adev->pio_mode - XFER_PIO_0;
    struct pci_dev *dev	= to_pci_dev(ap->host->dev);
    u16 idetm_data;
    int control = 0;

    /*
     *	See Intel Document 298600-004 for the timing programing rules
     *	for PIIX/ICH. Note that the early PIIX does not have the slave
     *	timing port at 0x44. The Radisys is a relative of the PIIX
     *	but not the same so be careful.
     */

    static const	 /* ISP  RTC */
    u8 timings[][2]	= { { 0, 0 },	/* Check me */
        { 0, 0 },
        { 1, 1 },
        { 2, 2 },
        { 3, 3 },
    };

    if (pio > 0)
        control |= 1;	/* TIME1 enable */
    if (ata_pio_need_iordy(adev))
        control |= 2;	/* IE IORDY */

    pci_read_config_word(dev, 0x40, &idetm_data);

    /* Enable IE and TIME as appropriate. Clear the other
       drive timing bits */
    idetm_data &= 0xCCCC;
    idetm_data |= (control << (4 * adev->devno));
    idetm_data |= (timings[pio][0] << 12) |
                  (timings[pio][1] << 8);
    pci_write_config_word(dev, 0x40, idetm_data);

    /* Track which port is configured */
    ap->private_data = adev;
}

static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
    unsigned int pio	= adev->pio_mode - XFER_PIO_0;
    struct pci_dev *dev	= to_pci_dev(ap->host_set->dev);
    unsigned int is_slave	= (adev->devno != 0);
    unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
    unsigned int slave_port	= 0x44;
    u16 master_data;
    u8 slave_data;

    static const	 /* ISP  RTC */
    u8 timings[][2]	= { { 0, 0 },
        { 0, 0 },
        { 1, 0 },
        { 2, 1 },
        { 2, 3 },
    };

    pci_read_config_word(dev, master_port, &master_data);
    if (is_slave) {
        master_data |= 0x4000;
        /* enable PPE, IE and TIME */
        master_data |= 0x0070;
        pci_read_config_byte(dev, slave_port, &slave_data);
        slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
        slave_data |=
            (timings[pio][0] << 2) |
            (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
    } else {
        master_data &= 0xccf8;
        /* enable PPE, IE and TIME */
        master_data |= 0x0007;
        master_data |=
            (timings[pio][0] << 12) |
            (timings[pio][1] << 8);
    }
    pci_write_config_word(dev, master_port, master_data);
    if (is_slave)
        pci_write_config_byte(dev, slave_port, slave_data);
}

static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
{
    struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
    u16 t1 = 0;
    u8 drive_pci = 0x40 + drive->dn * 2;

    const u16 pio_timings[]   = { 0x000, 0x607, 0x404, 0x303, 0x301 };
    const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };

    pci_read_config_word(dev, drive_pci, &t1);

    /* clear active/recovery timings */
    t1 &= ~0x070f;
    if (mode >= XFER_MW_DMA_0) {
        if (chipset_family > ATA_16)
            t1 &= ~0x8000;	/* disable UDMA */
        t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
    } else
        t1 |= pio_timings[mode - XFER_PIO_0];

    pci_write_config_word(dev, drive_pci, t1);
}