C++ pci_request_region函数代码示例

static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
{
	if (pci_request_region(dev, 2, "priv 2 regs"))
		goto err1;
	if (pci_request_region(dev, 0, "priv 1 regs"))
		goto err2;

	pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",
			p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));

	if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
		goto err3;

	if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
		goto err4;

	return 0;

err4:
	iounmap(adapter->p1_mmio);
	adapter->p1_mmio = NULL;
err3:
	pci_release_region(dev, 0);
err2:
	pci_release_region(dev, 2);
err1:
	return -ENOMEM;
}

static int bcwc_pci_reserve_mem(struct bcwc_private *dev_priv)
{
	unsigned long start;
	unsigned long len;
	int ret;

	/* Reserve resources */
	ret = pci_request_region(dev_priv->pdev, BCWC_PCI_S2_IO, "S2 IO");
	if (ret) {
		dev_err(&dev_priv->pdev->dev, "Failed to request S2 IO\n");
		return ret;
	}

	ret = pci_request_region(dev_priv->pdev, BCWC_PCI_S2_MEM, "S2 MEM");
	if (ret) {
		dev_err(&dev_priv->pdev->dev, "Failed to request S2 MEM\n");
		return ret;
	}

	ret = pci_request_region(dev_priv->pdev, BCWC_PCI_ISP_IO, "ISP IO");
	if (ret) {
		dev_err(&dev_priv->pdev->dev, "Failed to request ISP IO\n");
		return ret;
	}

	/* S2 IO */
	start = pci_resource_start(dev_priv->pdev, BCWC_PCI_S2_IO);
	len = pci_resource_len(dev_priv->pdev, BCWC_PCI_S2_IO);
	dev_priv->s2_io = ioremap_nocache(start, len);
	dev_priv->s2_io_len = len;

	/* S2 MEM */
	start = pci_resource_start(dev_priv->pdev, BCWC_PCI_S2_MEM);
	len = pci_resource_len(dev_priv->pdev, BCWC_PCI_S2_MEM);
	dev_priv->s2_mem = ioremap_nocache(start, len);
	dev_priv->s2_mem_len = len;

	/* ISP IO */
	start = pci_resource_start(dev_priv->pdev, BCWC_PCI_ISP_IO);
	len = pci_resource_len(dev_priv->pdev, BCWC_PCI_ISP_IO);
	dev_priv->isp_io = ioremap_nocache(start, len);
	dev_priv->isp_io_len = len;

	dev_info(&dev_priv->pdev->dev,
		 "Allocated S2 regs (BAR %d). %u bytes at 0x%p",
		 BCWC_PCI_S2_IO, dev_priv->s2_io_len, dev_priv->s2_io);

	dev_info(&dev_priv->pdev->dev,
		 "Allocated S2 mem (BAR %d). %u bytes at 0x%p",
		 BCWC_PCI_S2_MEM, dev_priv->s2_mem_len, dev_priv->s2_mem);

	dev_info(&dev_priv->pdev->dev,
		 "Allocated ISP regs (BAR %d). %u bytes at 0x%p",
		 BCWC_PCI_ISP_IO, dev_priv->isp_io_len, dev_priv->isp_io);

	pci_set_master(dev_priv->pdev);

	return 0;
}

int my_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
{
    printk(KERN_INFO "probe: bus->number: %2.x driver_data: %lu pci_slot: %x pci_func: %x\n", pdev->bus->number, id->driver_data, 
	PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));

    int en = pci_enable_device(pdev);
    if (en < 0) {
	return en;
    }
    int req_reg = pci_request_region(pdev, 0, "res0");
    if (req_reg < 0) {
	return req_reg;
    }
    void* mem = pci_ioremap_bar(pdev, 0);
    pci_set_drvdata(pdev, mem);
    
    u32 bridge_id = readl(mem);
    u32 bridge_build = readl(mem + 0x0004);
    
    printk(KERN_INFO "id: %4x build %4x\n", bridge_id, bridge_build);
    
    int rok   = 2000 + ((bridge_build & 0xf0000000) >> 28);
    int mesic =        (bridge_build & 0x0f000000) >> 24;
    int den   =        (bridge_build & 0x00ff0000) >> 16;
    int hodina =       (bridge_build & 0x0000ff00) >> 8;
    int minuta =       (bridge_build & 0x000000ff) >> 0;
    printk(KERN_INFO "vyrobeno: rok: %i mesic: %i den: %i hodina: %i minuta %i\n", rok, mesic, den, hodina, minuta);
    printk(KERN_INFO "vyrobeno: %i.%i.%i %i:%i\n", den, mesic, rok, hodina, minuta);
    

    return 0;
}

/**
 * map_bars - Resource allocation for device I/O Memory and I/O Port.
 *            Maps physical address of PCI buffer to virtual kernel space.
 *
 * @param l_head: List that will hold mapped BARs
 * @param pdev:   Pci device description
 * @param bars:   Bitmask of BARs to be requested
 * @param name:   Desired memory region name suffix(or NULL if none)
 *
 * @note Linked list should be freed afterwards by unmap_bars!
 *
 * @return how many BARs were mapped - in case of success.
 * @return -EBUSY                    - in case of failure.
 */
int map_bars(struct list_head *l_head, struct pci_dev *pdev, int bars, char *name)
{
  char res_name[32] = "BAR";
  bar_map_t *mem = NULL;
  bar_map_t *memP, *tmpP;
  int i, bcntr = 0;
  void __iomem *ioaddr;

  INIT_LIST_HEAD(l_head);

  for (i = 0; i < 6; i++)
    if ( (bars & (1 << i)) && (pci_resource_len(pdev, i)) ) {
      memset(&res_name[3], 0, sizeof(res_name)-3);
      snprintf(&res_name[3], sizeof(res_name)-3, "%d_%s", i, (name)?:'\0');
      if (pci_request_region(pdev, i, res_name))
	goto err_out;
      /* we will treat I/O ports as if they were I/O memory */
      if ( !(ioaddr = pci_iomap(pdev, i, 0)) )
	goto err_out_iomap;
      if ( !(mem = kzalloc((sizeof *mem), GFP_KERNEL)) )
	goto err_out_alloc;
      mem->mem_bar   = i;
      mem->mem_pdev  = pdev;
      mem->mem_remap = ioaddr;
      mem->mem_len   = pci_resource_len(pdev, i);
      list_add_tail(&mem->mem_list/*new*/, l_head/*head*/);
      ++bcntr;
    }

int mhi_init_pcie_device(mhi_pcie_dev_info *mhi_pcie_dev)
{
	int ret_val = 0;
	long int sleep_time = 100000;
	struct pci_dev *pcie_device =
			(struct pci_dev *)mhi_pcie_dev->pcie_device;
	/* Enable the device */
	do {
		ret_val = pci_enable_device(mhi_pcie_dev->pcie_device);
		if (0 != ret_val) {
			mhi_log(MHI_MSG_ERROR,
				"Failed to enable pcie device ret_val %d\n",
				ret_val);
			mhi_log(MHI_MSG_ERROR,
				"Sleeping for ~ %li uS, and retrying.\n",
				sleep_time);
			usleep(sleep_time);
		}
	} while (ret_val != 0);

	mhi_log(MHI_MSG_INFO, "Successfully enabled pcie device.\n");

	mhi_pcie_dev->core.bar0_base =
		(uintptr_t)ioremap_nocache(pci_resource_start(pcie_device, 0),
			pci_resource_len(pcie_device, 0));
	mhi_pcie_dev->core.bar0_end = mhi_pcie_dev->core.bar0_base +
		pci_resource_len(pcie_device, 0);
	mhi_pcie_dev->core.bar2_base =
		(uintptr_t)ioremap_nocache(pci_resource_start(pcie_device, 2),
			pci_resource_len(pcie_device, 2));
	mhi_pcie_dev->core.bar2_end = mhi_pcie_dev->core.bar2_base +
		pci_resource_len(pcie_device, 2);

	if (0 == mhi_pcie_dev->core.bar0_base) {
		mhi_log(MHI_MSG_ERROR,
			"Failed to register for pcie resources\n");
		goto mhi_pcie_read_ep_config_err;
	}

	mhi_log(MHI_MSG_INFO, "Device BAR0 address is at 0x%llx\n",
			mhi_pcie_dev->core.bar0_base);
	ret_val = pci_request_region(pcie_device, 0, mhi_pcie_driver.name);
	if (ret_val)
		mhi_log(MHI_MSG_ERROR, "Could not request BAR0 region\n");

	mhi_pcie_dev->core.manufact_id = pcie_device->vendor;
	mhi_pcie_dev->core.dev_id = pcie_device->device;

	if (mhi_pcie_dev->core.manufact_id != MHI_PCIE_VENDOR_ID ||
			mhi_pcie_dev->core.dev_id != MHI_PCIE_DEVICE_ID) {
		mhi_log(MHI_MSG_ERROR, "Incorrect device/manufacturer ID\n");
		goto mhi_device_list_error;
	}
	/* We need to ensure that the link is stable before we kick off MHI */
	return 0;
mhi_device_list_error:
	pci_disable_device(pcie_device);
mhi_pcie_read_ep_config_err:
	return -EIO;
}

static int __devinit tc86c001_init_one(struct pci_dev *dev,
				       const struct pci_device_id *id)
{
	int rc;

	rc = pci_enable_device(dev);
	if (rc)
		goto out;

	rc = pci_request_region(dev, 5, DRV_NAME);
	if (rc) {
		printk(KERN_ERR DRV_NAME ": system control regs already in use");
		goto out_disable;
	}

	rc = ide_pci_init_one(dev, &tc86c001_chipset, NULL);
	if (rc)
		goto out_release;

	goto out;

out_release:
	pci_release_region(dev, 5);
out_disable:
	pci_disable_device(dev);
out:
	return rc;
}

/* the PCI probing function */
int virtio_pci_legacy_probe(struct virtio_pci_device *vp_dev)
{
	struct pci_dev *pci_dev = vp_dev->pci_dev;
	int rc;

	/* We only own devices >= 0x1000 and <= 0x103f: leave the rest. */
	if (pci_dev->device < 0x1000 || pci_dev->device > 0x103f)
		return -ENODEV;

	if (pci_dev->revision != VIRTIO_PCI_ABI_VERSION) {
		printk(KERN_ERR "virtio_pci: expected ABI version %d, got %d\n",
		       VIRTIO_PCI_ABI_VERSION, pci_dev->revision);
		return -ENODEV;
	}

	rc = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64));
	if (rc) {
		rc = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
	} else {
		/*
		 * The virtio ring base address is expressed as a 32-bit PFN,
		 * with a page size of 1 << VIRTIO_PCI_QUEUE_ADDR_SHIFT.
		 */
		dma_set_coherent_mask(&pci_dev->dev,
				DMA_BIT_MASK(32 + VIRTIO_PCI_QUEUE_ADDR_SHIFT));
	}

	if (rc)
		dev_warn(&pci_dev->dev, "Failed to enable 64-bit or 32-bit DMA.  Trying to continue, but this might not work.\n");

	rc = pci_request_region(pci_dev, 0, "virtio-pci-legacy");
	if (rc)
		return rc;

	rc = -ENOMEM;
	vp_dev->ioaddr = pci_iomap(pci_dev, 0, 0);
	if (!vp_dev->ioaddr)
		goto err_iomap;

	vp_dev->isr = vp_dev->ioaddr + VIRTIO_PCI_ISR;

	/* we use the subsystem vendor/device id as the virtio vendor/device
	 * id.  this allows us to use the same PCI vendor/device id for all
	 * virtio devices and to identify the particular virtio driver by
	 * the subsystem ids */
	vp_dev->vdev.id.vendor = pci_dev->subsystem_vendor;
	vp_dev->vdev.id.device = pci_dev->subsystem_device;

	vp_dev->vdev.config = &virtio_pci_config_ops;

	vp_dev->config_vector = vp_config_vector;
	vp_dev->setup_vq = setup_vq;
	vp_dev->del_vq = del_vq;

	return 0;

err_iomap:
	pci_release_region(pci_dev, 0);
	return rc;
}

/*************************************************************************/ /*!
@Function       OSPCIResumeDev
@Description    Prepare a PCI device to be resumed by power management
@Input          hPVRPCI                 PCI device handle
@Return	        PVRSRV_ERROR	        Services error code
*/ /**************************************************************************/
PVRSRV_ERROR OSPCIResumeDev(PVRSRV_PCI_DEV_HANDLE hPVRPCI)
{
	PVR_PCI_DEV *psPVRPCI = (PVR_PCI_DEV *)hPVRPCI;
	int err;
	int i;

	err = pci_set_power_state(psPVRPCI->psPCIDev, pci_choose_state(psPVRPCI->psPCIDev, PMSG_ON));
	switch(err)
	{
		case 0:
			break;
		case -EIO:
			printk(KERN_ERR "OSPCIResumeDev: device doesn't support PCI PM");
			break;
		case -EINVAL:
			printk(KERN_ERR "OSPCIResumeDev: can't enter requested power state");
			return PVRSRV_ERROR_UNKNOWN_POWER_STATE;
		default:
			printk(KERN_ERR "OSPCIResumeDev: pci_set_power_state failed (%d)", err);
			return PVRSRV_ERROR_UNKNOWN_POWER_STATE;
	}

#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38))
	pci_restore_state(psPVRPCI->psPCIDev);
#else
	err = pci_restore_state(psPVRPCI->psPCIDev);
	if (err != 0)
	{
		printk(KERN_ERR "OSPCIResumeDev: pci_restore_state failed (%d)", err);
		return PVRSRV_ERROR_PCI_CALL_FAILED;
	}
#endif
	err = pci_enable_device(psPVRPCI->psPCIDev);
	if (err != 0)
	{
		printk(KERN_ERR "OSPCIResumeDev: Couldn't enable device (%d)", err);
		return PVRSRV_ERROR_PCI_CALL_FAILED;
	}

	if (psPVRPCI->ePCIFlags & HOST_PCI_INIT_FLAG_BUS_MASTER)	/* PRQA S 3358 */ /* misuse of enums */
		pci_set_master(psPVRPCI->psPCIDev);

	/* Restore the PCI resource tracking array */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
	{
		if (psPVRPCI->abPCIResourceInUse[i])
		{
			err = pci_request_region(psPVRPCI->psPCIDev, i, PVRSRV_MODNAME);
			if (err != 0)
			{
				printk(KERN_ERR "OSPCIResumeDev: pci_request_region_failed (region %d, error %d)", i, err);
			}
		}
	}

	return PVRSRV_OK;
}

static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
							const char *name)
{
	int err = pci_request_region(dev, 5, name);

	if (err)
		printk(KERN_ERR "%s: system control regs already in use", name);
	return err;
}

static int __init cs5535_gpio_probe(struct pci_dev *pdev,
		const struct pci_device_id *pci_id)
{
	int err;
	ulong mask_orig = mask;

	/* There are two ways to get the GPIO base address; one is by
	 * fetching it from MSR_LBAR_GPIO, the other is by reading the
	 * PCI BAR info.  The latter method is easier (especially across
	 * different architectures), so we'll stick with that for now.  If
	 * it turns out to be unreliable in the face of crappy BIOSes, we
	 * can always go back to using MSRs.. */

	err = pci_enable_device_io(pdev);
	if (err) {
		dev_err(&pdev->dev, "can't enable device IO\n");
		goto done;
	}

	err = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
	if (err) {
		dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
		goto done;
	}

	/* set up the driver-specific struct */
	cs5535_gpio_chip.base = pci_resource_start(pdev, GPIO_BAR);
	cs5535_gpio_chip.pdev = pdev;
	spin_lock_init(&cs5535_gpio_chip.lock);

	dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", GPIO_BAR,
			(unsigned long long) cs5535_gpio_chip.base);

	/* mask out reserved pins */
	mask &= 0x1F7FFFFF;

	/* do not allow pin 28, Power Button, as there's special handling
	 * in the PMC needed. (note 12, p. 48) */
	mask &= ~(1 << 28);

	if (mask_orig != mask)
		dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
				mask_orig, mask);

	/* finally, register with the generic GPIO API */
	err = gpiochip_add(&cs5535_gpio_chip.chip);
	if (err)
		goto release_region;

	dev_info(&pdev->dev, DRV_NAME ": GPIO support successfully loaded.\n");
	return 0;

release_region:
	pci_release_region(pdev, GPIO_BAR);
done:
	return err;
}

/*************************************************************************/ /*!
@Function       OSPCIAddrRangeFunc
@Description    Internal support function for various address range related 
                functions
@Input          eFunc                   Function to perform
@Input          hPVRPCI                 PCI device handle
@Input          ui32Index               Address range index
@Return		IMG_UINT32              Function dependent value
*/ /**************************************************************************/
static IMG_UINT32 OSPCIAddrRangeFunc(enum HOST_PCI_ADDR_RANGE_FUNC eFunc,
				     PVRSRV_PCI_DEV_HANDLE hPVRPCI,
				     IMG_UINT32 ui32Index)
{
	PVR_PCI_DEV *psPVRPCI = (PVR_PCI_DEV *)hPVRPCI;

	if (ui32Index >= DEVICE_COUNT_RESOURCE)
	{
		printk(KERN_ERR "OSPCIAddrRangeFunc: Index out of range");
		return 0;
	}

	switch (eFunc)
	{
		case HOST_PCI_ADDR_RANGE_FUNC_LEN:
		{
			return pci_resource_len(psPVRPCI->psPCIDev, ui32Index);
		}
		case HOST_PCI_ADDR_RANGE_FUNC_START:
		{
			return pci_resource_start(psPVRPCI->psPCIDev, ui32Index);
		}
		case HOST_PCI_ADDR_RANGE_FUNC_END:
		{
			return pci_resource_end(psPVRPCI->psPCIDev, ui32Index);
		}
		case HOST_PCI_ADDR_RANGE_FUNC_REQUEST:
		{
			int err = pci_request_region(psPVRPCI->psPCIDev, (IMG_INT)ui32Index, PVRSRV_MODNAME);
			if (err != 0)
			{
				printk(KERN_ERR "OSPCIAddrRangeFunc: pci_request_region_failed (%d)", err);
				return 0;
			}
			psPVRPCI->abPCIResourceInUse[ui32Index] = IMG_TRUE;
			return 1;
		}
		case HOST_PCI_ADDR_RANGE_FUNC_RELEASE:
		{
			if (psPVRPCI->abPCIResourceInUse[ui32Index])
			{
				pci_release_region(psPVRPCI->psPCIDev, (IMG_INT)ui32Index);
				psPVRPCI->abPCIResourceInUse[ui32Index] = IMG_FALSE;
			}
			return 1;
		}
		default:
		{
			printk(KERN_ERR "OSPCIAddrRangeFunc: Unknown function");
			break;
		}
	}

	return 0;
}

static int asd_map_memio(struct asd_ha_struct *asd_ha)
{
	int err, i;
	struct asd_ha_addrspace *io_handle;

	asd_ha->iospace = 0;
	for (i = 0; i < 3; i += 2) {
		io_handle = &asd_ha->io_handle[i==0?0:1];
		io_handle->start = pci_resource_start(asd_ha->pcidev, i);
		io_handle->len   = pci_resource_len(asd_ha->pcidev, i);
		io_handle->flags = pci_resource_flags(asd_ha->pcidev, i);
		err = -ENODEV;
		if (!io_handle->start || !io_handle->len) {
			asd_printk("MBAR%d start or length for %s is 0.\n",
				   i==0?0:1, pci_name(asd_ha->pcidev));
			goto Err;
		}
		err = pci_request_region(asd_ha->pcidev, i, ASD_DRIVER_NAME);
		if (err) {
			asd_printk("couldn't reserve memory region for %s\n",
				   pci_name(asd_ha->pcidev));
			goto Err;
		}
		if (io_handle->flags & IORESOURCE_CACHEABLE)
			io_handle->addr = ioremap(io_handle->start,
						  io_handle->len);
		else
			io_handle->addr = ioremap_nocache(io_handle->start,
							  io_handle->len);
		if (!io_handle->addr) {
			asd_printk("couldn't map MBAR%d of %s\n", i==0?0:1,
				   pci_name(asd_ha->pcidev));
			err = -ENOMEM;
			goto Err_unreq;
		}
	}

	return 0;
Err_unreq:
	pci_release_region(asd_ha->pcidev, i);
Err:
	if (i > 0) {
		io_handle = &asd_ha->io_handle[0];
		iounmap(io_handle->addr);
		pci_release_region(asd_ha->pcidev, 0);
	}
	return err;
}

/* enable SRAM if sram detected */
static void sram_init(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	void __iomem		*base = NULL;
	void __iomem		*addr = NULL;

	if (!hcd->has_sram)
		return;
	ehci->sram_addr = pci_resource_start(pdev, 1);
	ehci->sram_size = pci_resource_len(pdev, 1);
	ehci_info(ehci, "Found HCD SRAM at %x size:%x\n",
		ehci->sram_addr, ehci->sram_size);

	if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
		ehci_warn(ehci, "SRAM request failed\n");
		hcd->has_sram = 0;
		return;
	} else if (!dma_declare_coherent_memory(&pdev->dev, ehci->sram_addr,
			ehci->sram_addr, ehci->sram_size, DMA_MEMORY_MAP)) {
		ehci_warn(ehci, "SRAM DMA declare failed\n");
		pci_release_region(pdev, 1);
		hcd->has_sram = 0;
		return;
	}

	/* initialize SRAM to 0 to avoid ECC errors during entry into D0 */
	base = ioremap_nocache(ehci->sram_addr, ehci->sram_size);
	if (base == NULL) {
		ehci_warn(ehci, "SRAM init: ioremap failed\n");
		return;
	}

	addr = base;

	while (addr < base + ehci->sram_size) {
		writel(0x0, addr);
		addr = addr + 4;
	}

	iounmap(base);
}

static int mem_alloc(struct pci_dev *pdev, uintptr_t *phy_addr,
		void **virt_addr, int bar)
{
	void __iomem *mem;
	int ret = 0;
	unsigned long start = 0, len;

	/* dedicate isolated memory region */
	start = pci_resource_start(pdev, bar);
	len = pci_resource_len(pdev, bar);
	if (!start || !len) {
		dev_err(&pdev->dev, "bar %d address not set\n", bar);
		ret = -EINVAL;
		goto err;
	}

	ret = pci_request_region(pdev, bar, "intel_mcu");
	if (ret) {
		dev_err(&pdev->dev,
				"failed to request psh region 0x%lx-0x%lx\n",
				start,
				(unsigned long)pci_resource_end(pdev, bar));
		goto err;
	}

	mem = ioremap_nocache(start, len);
	if (!mem) {
		dev_err(&pdev->dev, "can not ioremap app imr address\n");
		ret = -EINVAL;
		goto err_ioremap;
	}

	*phy_addr = start;
	*virt_addr = (void *)mem;
	return 0;

err_ioremap:
	pci_release_region(pdev, bar);
err:
	return ret;
}

static int serial_hsu_pci_port_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	struct uart_hsu_port *up;
	int ret, port, hw_type;
	resource_size_t start, len;

	start = pci_resource_start(pdev, 0);
	len = pci_resource_len(pdev, 0);

	dev_info(&pdev->dev,
		"FUNC: %d driver: %ld addr:%lx len:%lx\n",
		PCI_FUNC(pdev->devfn), ent->driver_data,
		(unsigned long) start, (unsigned long) len);

	port = intel_mid_hsu_func_to_port(PCI_FUNC(pdev->devfn));
	if (port == -1)
		return 0;

	ret = pci_enable_device(pdev);
	if (ret)
		return ret;

	ret = pci_request_region(pdev, 0, "hsu");
	if (ret)
		goto err;

	up = serial_hsu_port_setup(&pdev->dev, port, start, len,
			pdev->irq);
	if (IS_ERR(up))
		goto err;

	pci_set_drvdata(pdev, up);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);
	return 0;
err:
	pci_disable_device(pdev);
	return ret;
}