C++ pci_read_config32函数代码示例

void init_bootmode_straps(void)
{
#ifdef __PRE_RAM__
    u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
    u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
    u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
    u32 gp_lvl = inl(gpio_base + GP_LVL);
    u32 flags = 0;

    /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
    if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
        flags |= (1 << FLAG_SPI_WP);
    /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
    if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
        flags |= (1 << FLAG_REC_MODE);
    /* Developer: GPIO17 = KBC3_DVP_MODE, active high */
    if (gp_lvl & (1 << GPIO_DEV_MODE))
        flags |= (1 << FLAG_DEV_MODE);

    pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}

static void ide_init(struct device *dev)
{
	struct southbridge_nvidia_ck804_config *conf;
	u32 dword;
	u16 word;
	u8 byte;

	conf = dev->chip_info;

	word = pci_read_config16(dev, 0x50);
	/* Ensure prefetch is disabled. */
	word &= ~((1 << 15) | (1 << 13));
	if (conf->ide1_enable) {
		/* Enable secondary IDE interface. */
		word |= (1 << 0);
		printk(BIOS_DEBUG, "IDE1 \t");
	}
	if (conf->ide0_enable) {
		/* Enable primary IDE interface. */
		word |= (1 << 1);
		printk(BIOS_DEBUG, "IDE0\n");
	}

	word |= (1 << 12);
	word |= (1 << 14);

	pci_write_config16(dev, 0x50, word);

	byte = 0x20;		/* Latency: 64 --> 32 */
	pci_write_config8(dev, 0xd, byte);

	dword = pci_read_config32(dev, 0xf8);
	dword |= 12;
	pci_write_config32(dev, 0xf8, dword);

#if CONFIG_PCI_ROM_RUN
	pci_dev_init(dev);
#endif
}

static void vga_init(device_t dev)
{
	u8 reg8;

	mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);

	//*
	pci_write_config8(dev, 0x04, 0x07);
	pci_write_config8(dev, 0x3e, 0x02);
	pci_write_config8(dev, 0x0d, 0x40);
	pci_write_config32(dev, 0x10, 0xa0000008);
	pci_write_config32(dev, 0x14, 0xdd000000);
	pci_write_config8(dev, 0x3c, 0x0b);
	//*/

	printk(BIOS_DEBUG, "Initializing VGA...\n");

	pci_dev_init(dev);

	if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;

	printk(BIOS_DEBUG, "Enable VGA console\n");
	vga_enable_console();

	/* It's not clear if these need to be programmed before or after
	 * the VGA bios runs. Try both, clean up later */
	/* Set memory rate to 200MHz */
	outb(0x3d, CRTM_INDEX);
	reg8 = inb(CRTM_DATA);
	reg8 &= 0x0f;
	reg8 |= (0x3 << 4);
	outb(0x3d, CRTM_INDEX);
	outb(reg8, CRTM_DATA);

	/* Set framebuffer size to 32mb */
	reg8 = (32 / 4);
	outb(0x39, SR_INDEX);
	outb(reg8, SR_DATA);
}

static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
				   unsigned device)
{
	u8 access_cntl;

	access_cntl = pci_read_config8(dev, 0x80);

	/* Enable writes to protected registers. */
	pci_write_config8(dev, 0x80, access_cntl | 1);

	if (!vendor || !device) {
		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
				   pci_read_config32(dev, PCI_VENDOR_ID));
	} else {
		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
				   ((device & 0xffff) << 16) | (vendor &
								0xffff));
	}

	/* Restore protection. */
	pci_write_config8(dev, 0x80, access_cntl);
}

void intel_pch_finalize_smm(void)
{
	/* Set SPI opcode menu */
	RCBA16(0x3894) = SPI_OPPREFIX;
	RCBA16(0x3896) = SPI_OPTYPE;
	RCBA32(0x3898) = SPI_OPMENU_LOWER;
	RCBA32(0x389c) = SPI_OPMENU_UPPER;

	/* Lock SPIBAR */
	RCBA32_OR(0x3804, (1 << 15));

#if CONFIG_SPI_FLASH_SMM
	/* Re-init SPI driver to handle locked BAR */
	spi_init();
#endif

	/* TCLOCKDN: TC Lockdown */
	RCBA32_OR(0x0050, (1 << 31));

	/* BIOS Interface Lockdown */
	RCBA32_OR(0x3410, (1 << 0));

	/* Function Disable SUS Well Lockdown */
	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));

	/* Global SMI Lock */
	pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);

	/* GEN_PMCON Lock */
	pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));

	/* R/WO registers */
	RCBA32(0x21a4) = RCBA32(0x21a4);
	pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
		    pci_read_config32(PCI_DEV(0, 27, 0), 0x74));

	/* Indicate finalize step with post code */
	outb(POST_OS_BOOT, 0x80);
}

static void
chrome_init(struct device *dev)
{
	uint32_t fb_size, fb_address;

	fb_size = k8m890_host_fb_size_get();
	if (!fb_size) {
		printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
			       " ramcontroller!\n");
		return;
	}

	fb_address = pci_read_config32(dev, 0x10);
	fb_address &= ~0x0F;
	if (!fb_address) {
		printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
		return;
	}

	printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
		    fb_size, fb_address);

	//k8m890_host_fb_direct_set(fb_address);

#if CONFIG_VGA
	/* Now set up the VGA console */
	vga_io_init(); /* Enable full IO access */

	chrome_vga_init(dev);

	vga_textmode_init();

	printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");

	/* if we don't have console, at least print something... */
	vga_line_write(0, "Chrome VGA Textmode initialized.");
#endif /* CONFIG_VGA */
}

static void ide_init(struct device *dev)
{
	struct southbridge_amd_sb800_config *conf;
	/* Enable ide devices so the linux ide driver will work */
	u32 dword;
	u8 byte;

	conf = dev->chip_info;

	/* RPR9.1 disable MSI */
	/* TODO: For A14, it should set as 1. I doubt it. */
	dword = pci_read_config32(dev, 0x70);
	dword &= ~(1 << 16);
	pci_write_config32(dev, 0x70, dword);

	/* Ultra DMA mode */
	/* enable UDMA */
	byte = pci_read_config8(dev, 0x54);
	byte |= 1 << 0;
	pci_write_config8(dev, 0x54, byte);

	/* Enable I/O Access&& Bus Master */
	dword = pci_read_config16(dev, 0x4);
	dword |= 1 << 2;
	pci_write_config16(dev, 0x4, dword);

	/* set ide as primary, if you want to boot from IDE, you'd better set it
	 * in mainboard/Config.lb */
	if (conf->boot_switch_sata_ide == 1) {
		byte = pci_read_config8(dev, 0xAD);
		byte |= 1 << 4;
		pci_write_config8(dev, 0xAD, byte);
	}

#if CONFIG_PCI_ROM_RUN == 1
	pci_dev_init(dev);
#endif
}

static void enable_hpet(struct device *dev)
{
	const unsigned long hpet_address = 0xfed00000;

	uint32_t dword;
	uint32_t code = (0 & 0x3);

	dword = pci_read_config32(dev, GEN_CNTL);
	dword |= (1 << 17); /* enable hpet */

	/* Bits [16:15]  Memory Address Range
	 *	    00   FED0_0000h - FED0_03FFh
	 *	    01   FED0_1000h - FED0_13FFh
	 *	    10   FED0_2000h - FED0_23FFh
	 *	    11   FED0_3000h - FED0_33FFh
	 */

	dword &= ~(3 << 15); /* clear it */
	dword |= (code<<15);
	pci_write_config32(dev, GEN_CNTL, dword);

	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
}

static void native_init(struct device *dev)
{
	struct resource *lfb_res;
	struct resource *pio_res;
	u32 physbase;
	struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
	struct northbridge_intel_x4x_config *conf = dev->chip_info;

	lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
	pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
	physbase = pci_read_config32(dev, 0x5c) & ~0xf;

	if (gtt_res && gtt_res->base) {
		printk(BIOS_SPEW,
			"Initializing VGA without OPROM. MMIO 0x%llx\n",
			gtt_res->base);
		intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
			physbase, pio_res->base, lfb_res->base);
	}

	/* Linux relies on VBT for panel info.  */
	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");
}

unsigned long acpi_fill_madt(unsigned long current)
{
	device_t dev;
	u32 dword;
	u32 gsi_base=0;
	/* create all subtables for processors */
	current = acpi_create_madt_lapics(current);

	/* Write SB700 IOAPIC, only one */
	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
					   IO_APIC_ADDR, gsi_base);
	/* IOAPIC on rs5690 */
	gsi_base += 24;		/* SB700 has 24 IOAPIC entries. */
	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
	if (dev) {
		pci_write_config32(dev, 0xF8, 0x1);
		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1,
						   dword, gsi_base);
	}


	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
						current, 0, 0, 2, 0);
	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
						current, 0, 9, 9, 0xF);
	/* 0: mean bus 0--->ISA */
	/* 0: PIC 0 */
	/* 2: APIC 2 */
	/* 5 mean: 0101 --> Edge-triggered, Active high */

	/* create all subtables for processors */
	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
	/* 1: LINT1 connect to NMI */

	return current;
}

static void sdram_set_registers(const struct mem_controller *ctrl)
{
	static const u32 register_values[] = {
		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
		PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG,
		PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
		PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
		PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
		PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
	};
	int i;

	for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
		device_t dev;
		u32 where;
		u32 reg;
		dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
		where = register_values[i] & 0xff;
		reg = pci_read_config32(dev, where);
		reg &= register_values[i+1];
		reg |= register_values[i+2];
		pci_write_config32(dev, where, reg);
	}
}

static void usb_init(struct device *dev)
{
        printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");

//-------------- enable USB1.1 (SiS7001) -------------------------
{
        uint8_t  temp8;
        int i=0;

	 while(SiS_SiS7001_init[i][0] != 0)
	 {				temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
					temp8 &= SiS_SiS7001_init[i][1];
					temp8 |= SiS_SiS7001_init[i][2];
					pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
					i++;
	 };
}
//-----------------------------------------------------------

#if DEBUG_USB
{
        int i;

        printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");

        for(i=0;i<0xff;i+=4){
                if((i%16)==0)
                        printk(BIOS_DEBUG, "\n%02x: ", i);
                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
        }
        printk(BIOS_DEBUG, "\n");
}
#endif
        printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}

/*
 * set gpio40 gfx
 */
static void set_gpio40_gfx(void)
{
	u8 byte;
//	u16 word;
	u32 dword;
	struct device *sm_dev;
	/* disable the GPIO40 as CLKREQ2# function */
	byte = pm_ioread(0xd3);
	byte &= ~(1 << 7);
	pm_iowrite(0xd3, byte);

	/* disable the GPIO40 as CLKREQ3# function */
	byte = pm_ioread(0xd4);
	byte &= ~(1 << 0);
	pm_iowrite(0xd4, byte);

	/* enable pull up for GPIO68 */
	byte = pm2_ioread(0xf1);
	byte &=	~(1 << 4);
	pm2_iowrite(0xf1, byte);

	/* access the smbus extended register */
	sm_dev = pcidev_on_root(0x14, 0);

	/* set the gfx to 1x16 lanes */
	printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
	/* when the gpio40 is configured as GPIO, this will enable the output */
	pci_write_config32(sm_dev, 0xf8, 0x4);
	dword = pci_read_config32(sm_dev, 0xfc);
	dword &= ~(1 << 10);

        /* When the gpio40 is configured as GPIO, this will represent the output value*/
	/* 1 :enable two x8  , 0 : master slot enable only */
	dword &=  ~(1 << 26);
	pci_write_config32(sm_dev, 0xfc, dword);
}

static void ide_init(struct device *dev)
{
	struct southbridge_amd_sb700_config *conf;
	/* Enable ide devices so the linux ide driver will work */
	u32 dword;
	u8 byte;

	conf = dev->chip_info;

	/* RPR9.1 disable MSI */
	/* TODO: For A14, it should set as 1. I doubt it. */
	dword = pci_read_config32(dev, 0x70);
	dword &= ~(1 << 16);
	pci_write_config32(dev, 0x70, dword);

	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
	byte = pci_read_config8(dev, 0x54);
	byte |= 0xf;
	pci_write_config8(dev, 0x54, byte);

	/* Enable I/O Access&& Bus Master */
	dword = pci_read_config16(dev, 0x4);
	dword |= 1 << 2;
	pci_write_config16(dev, 0x4, dword);

	/* set ide as primary, if you want to boot from IDE, you'd better set it
	 * in $vendor/$mainboard/devicetree.cb */


	if (conf->boot_switch_sata_ide == 1) {
		struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
		byte = pci_read_config8(sm_dev, 0xAD);
		byte |= 1 << 4;
		pci_write_config8(sm_dev, 0xAD, byte);
	}
}

void igd_compute_ggc(sysinfo_t *const sysinfo)
{
	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);

	const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
		sysinfo->ggc = 0x0002;
	else {
		u8 gfxsize;

		/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
		   2MB GTT + 2MB shadow GTT (0x0b00) else. */
		if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
			/* 4 for 32MB, default if not set in cmos */
			gfxsize = 4;
		}
		/* Handle invalid cmos settings */
		if (gfxsize > 12)
			gfxsize = 4;
		sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4);
		if (!(capid & (1 << (48 - 32))))
			sysinfo->ggc |= 0x0800;
	}
}