C++ omap_i2c_write_reg函数代码示例

static irqreturn_t
omap_i2c_rev1_isr(int this_irq, void *dev_id)
{
	struct omap_i2c_dev *dev = dev_id;
	u16 iv, w;

	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
	switch (iv) {
	case 0x00:	/* None */
		break;
	case 0x01:	/* Arbitration lost */
		dev_err(dev->dev, "Arbitration lost\n");
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
		break;
	case 0x02:	/* No acknowledgement */
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
		break;
	case 0x03:	/* Register access ready */
		omap_i2c_complete_cmd(dev, 0);
		break;
	case 0x04:	/* Receive data ready */
		if (dev->buf_len) {
			w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
			*dev->buf++ = w;
			dev->buf_len--;
			if (dev->buf_len) {
				*dev->buf++ = w >> 8;
				dev->buf_len--;
			}
		} else

static void __omap_i2c_init(struct omap_i2c_dev *dev)
{

	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);

	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);

	/* SCL low and high time values */
	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);

	/* Take the I2C module out of reset: */
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);

	/*
	 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
	 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
	 * udelay(1) will be enough to fix that.
	 */

	/*
	 * Don't write to this register if the IE state is 0 as it can
	 * cause deadlock.
	 */
	if (dev->iestate)
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
}

static int omap_i2c_reset(struct omap_i2c_dev *dev)
{
	unsigned long timeout;
	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
		/* Disable I2C controller before soft reset */
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
			omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
				~(OMAP_I2C_CON_EN));

		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
		/* For some reason we need to set the EN bit before the
		 * reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
			 SYSS_RESETDONE_MASK)) {
			if (time_after(jiffies, timeout)) {
				dev_warn(dev->dev, "timeout waiting "
						"for controller reset\n");
				return -ETIMEDOUT;
			}
			mdelay(1);
		}

		/* SYSC register is cleared by the reset; rewrite it */
		if (dev->rev == OMAP_I2C_REV_ON_2430) {

			omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
					   SYSC_AUTOIDLE_MASK);

		} else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
			dev->syscstate = SYSC_AUTOIDLE_MASK;
			dev->syscstate |= SYSC_ENAWAKEUP_MASK;
			dev->syscstate |= (SYSC_IDLEMODE_SMART <<
			      __ffs(SYSC_SIDLEMODE_MASK));
			dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
			      __ffs(SYSC_CLOCKACTIVITY_MASK));

			omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
							dev->syscstate);
		}
	}
	return 0;
}

static void omap_i2c_idle(struct omap_i2c_dev *dev)
{
	u16 iv;

	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
	if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
		omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
	else
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);

	if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
		iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
	} else {
		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);

		/* Flush posted write */
		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
	}
}

static void omap_i2c_unidle(struct omap_i2c_dev *dev)
{
	struct platform_device *pdev;
	struct omap_i2c_bus_platform_data *pdata;

	WARN_ON(!dev->idle);

	pdev = to_platform_device(dev->dev);
	pdata = pdev->dev.platform_data;

	pm_runtime_get_sync(&pdev->dev);

	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
		unsigned long delay;

		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);

		delay = jiffies + OMAP_I2C_TIMEOUT;
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG)
				& OMAP_I2C_SYSS_RDONE)) {
			if (time_after(jiffies, delay)) {
				dev_err(dev->dev, "omap i2c unidle timeout\n");
				return;
			}
			cpu_relax();
		}
	}
	dev->idle = 0;

	if (cpu_is_omap44xx() && dev->rev >= OMAP_I2C_REV_ON_4430) {
		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 0x6FFF);
		omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_SET, dev->iestate);
	} else {
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
	}
}

static void omap_i2c_idle(struct omap_i2c_dev *dev)
{
	struct omap_i2c_bus_platform_data *pdata;
	u16 iv;

	pdata = dev->dev->platform_data;

	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);

	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);

	if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
		iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
	} else {
		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);

		/* Flush posted write */
		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
	}
}

static void omap_i2c_idle(struct omap_i2c_dev *dev)
{
	u16 iv;

	WARN_ON(dev->idle);

	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
	if (dev->rev < OMAP_I2C_REV_2) {
		iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
	} else {
		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);

		/* Flush posted write before the dev->idle store occurs */
		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
	}
	dev->idle = 1;
	clk_disable(dev->fclk);
	clk_disable(dev->iclk);
}

/*
 * Bus Clear
 */
static int omap_i2c_bus_clear(struct omap_i2c_dev *dev)
{
	u16 w;

	/* Per the I2C specification, if we are stuck in a bus busy state
	 * we can attempt a bus clear to try and recover the bus by sending
	 * at least 9 clock pulses on SCL. Put the I2C in a test mode so it
	 * will output a continuous clock on SCL.
	 */
	w = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG,
		(OMAP_I2C_SYSTEST_ST_EN | OMAP_I2C_SYSTEST_TMODE_TEST));
	msleep(1);
	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, w);
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
	omap_i2c_reset(dev);
	omap_i2c_init(dev);
	return omap_i2c_wait_for_bb(dev);
}

static int omap_i2c_reset(struct omap_i2c_dev *dev)
{
	unsigned long timeout;
	u16 sysc;

	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
		sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);

		/* Disable I2C controller before soft reset */
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
			omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
				~(OMAP_I2C_CON_EN));

		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
		/* For some reason we need to set the EN bit before the
		 * reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
			 SYSS_RESETDONE_MASK)) {
			if (time_after(jiffies, timeout)) {
				dev_warn(dev->dev, "timeout waiting "
						"for controller reset\n");
				return -ETIMEDOUT;
			}
			msleep(1);
		}

		/* SYSC register is cleared by the reset; rewrite it */
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);

		if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
			/* Schedule I2C-bus monitoring on the next transfer */
			dev->bb_valid = 0;
		}
	}

	return 0;
}

static void omap_i2c_unidle(struct omap_i2c_dev *dev)
{
	WARN_ON(!dev->idle);

	clk_enable(dev->iclk);
	clk_enable(dev->fclk);
	if (cpu_is_omap34xx()) {
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
	}
	dev->idle = 0;
	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
}

static void omap_i2c_unidle(struct omap_i2c_dev *dev)
{
	if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
	}

	/*
	 * Don't write to this register if the IE state is 0 as it can
	 * cause deadlock.
	 */
	if (dev->iestate)
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
}

static irqreturn_t
omap_i2c_rev1_isr(int this_irq, void *dev_id)
{
	struct omap_i2c_dev *dev = dev_id;
	u16 iv, w;

	if (dev->idle)
		return IRQ_NONE;

	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
	switch (iv) {
	case 0x00:	/* None */
		break;
/* <-- [email protected] delete arbitration mechanism for solving mg touch suspend/resume issue*/		
#if 0		
	case 0x01:	/* Arbitration lost */
		dev_err(dev->dev, "Arbitration lost\n");
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
		break;
#endif		
/*  [email protected] delete arbitration mechanism for solving mg touch suspend/resume issue -->*/		
	case 0x02:	/* No acknowledgement */
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
		break;
	case 0x03:	/* Register access ready */
		omap_i2c_complete_cmd(dev, 0);
		break;
	case 0x04:	/* Receive data ready */
		if (dev->buf_len) {
			w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
			*dev->buf++ = w;
			dev->buf_len--;
			if (dev->buf_len) {
				*dev->buf++ = w >> 8;
				dev->buf_len--;
			}
		} else

static int omap_i2c_init(struct omap_i2c_dev *dev)
{
	u16 psc = 0, scll = 0, sclh = 0, buf = 0;
	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
	unsigned long fclk_rate = 12000000;
	unsigned long timeout;
	unsigned long internal_clk = 0;
	struct clk *fclk;

	if (dev->rev >= OMAP_I2C_REV_2) {
		/* Disable I2C controller before soft reset */
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
			omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
				~(OMAP_I2C_CON_EN));

		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
		/* For some reason we need to set the EN bit before the
		 * reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
			 SYSS_RESETDONE_MASK)) {
			if (time_after(jiffies, timeout)) {
				dev_warn(dev->dev, "timeout waiting "
						"for controller reset\n");
				return -ETIMEDOUT;
			}
			msleep(1);
		}

		/* SYSC register is cleared by the reset; rewrite it */
		if (dev->rev == OMAP_I2C_REV_ON_2430) {

			omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
					   SYSC_AUTOIDLE_MASK);

		} else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
			dev->syscstate = SYSC_AUTOIDLE_MASK;
			dev->syscstate |= SYSC_ENAWAKEUP_MASK;
			dev->syscstate |= (SYSC_IDLEMODE_SMART <<
			      __ffs(SYSC_SIDLEMODE_MASK));
			dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
			      __ffs(SYSC_CLOCKACTIVITY_MASK));

			omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
							dev->syscstate);
			/*
			 * Enabling all wakup sources to stop I2C freezing on
			 * WFI instruction.
			 * REVISIT: Some wkup sources might not be needed.
			 */
			dev->westate = OMAP_I2C_WE_ALL;
			omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
		}
	}
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);

	if (cpu_class_is_omap1()) {
		/*
		 * The I2C functional clock is the armxor_ck, so there's
		 * no need to get "armxor_ck" separately.  Now, if OMAP2420
		 * always returns 12MHz for the functional clock, we can
		 * do this bit unconditionally.
		 */
		fclk = clk_get(dev->dev, "fck");
		fclk_rate = clk_get_rate(fclk);
		clk_put(fclk);

		/* TRM for 5912 says the I2C clock must be prescaled to be
		 * between 7 - 12 MHz. The XOR input clock is typically
		 * 12, 13 or 19.2 MHz. So we should have code that produces:
		 *
		 * XOR MHz	Divider		Prescaler
		 * 12		1		0
		 * 13		2		1
		 * 19.2		2		1
		 */
		if (fclk_rate > 12000000)
			psc = fclk_rate / 12000000;
	}

	if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {

		/*
		 * HSI2C controller internal clk rate should be 19.2 Mhz for
		 * HS and for all modes on 2430. On 34xx we can use lower rate
		 * to get longer filter period for better noise suppression.
		 * The filter is iclk (fclk for HS) period.
		 */
		if (dev->speed > 400 || cpu_is_omap2430())
			internal_clk = 19200;
		else if (dev->speed > 100)
			internal_clk = 9600;
		else
			internal_clk = 4000;
		fclk = clk_get(dev->dev, "fck");
		fclk_rate = clk_get_rate(fclk) / 1000;
		clk_put(fclk);

		/* Compute prescaler divisor */
//.........这里部分代码省略.........

/*
 * Low level master read/write transaction.
 */
static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
			     struct i2c_msg *msg, int stop)
{
	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
	int r;
	u16 w;

	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
		msg->addr, msg->len, msg->flags, stop);

	if (msg->len == 0)
		return -EINVAL;

	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);

	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
	dev->buf = msg->buf;
	dev->buf_len = msg->len;

	omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);

	init_completion(&dev->cmd_complete);
	dev->cmd_err = 0;

	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
	if (msg->flags & I2C_M_TEN)
		w |= OMAP_I2C_CON_XA;
	if (!(msg->flags & I2C_M_RD))
		w |= OMAP_I2C_CON_TRX;
	if (stop)
		w |= OMAP_I2C_CON_STP;
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);

	r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
						      OMAP_I2C_TIMEOUT);
	dev->buf_len = 0;
	if (r < 0)
		return r;
	if (r == 0) {
		dev_err(dev->dev, "controller timed out\n");
		omap_i2c_init(dev);
		return -ETIMEDOUT;
	}

	if (likely(!dev->cmd_err))
		return 0;

	/* We have an error */
	if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
			    OMAP_I2C_STAT_XUDF)) {
		omap_i2c_init(dev);
		return -EIO;
	}

	if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
		if (msg->flags & I2C_M_IGNORE_NAK)
			return 0;
		if (stop) {
			w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
			w |= OMAP_I2C_CON_STP;
			omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
		}
		return -EREMOTEIO;
	}
	return -EIO;
}

static int omap_i2c_init(struct omap_i2c_dev *dev)
{
	u16 psc = 0;
	unsigned long fclk_rate = 12000000;
	unsigned long timeout;

	if (!dev->rev1) {
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
		/* For some reason we need to set the EN bit before the
		 * reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
			 OMAP_I2C_SYSS_RDONE)) {
			if (time_after(jiffies, timeout)) {
				dev_warn(dev->dev, "timeout waiting "
						"for controller reset\n");
				return -ETIMEDOUT;
			}
			msleep(1);
		}
	}
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);

	if (cpu_class_is_omap1()) {
		struct clk *armxor_ck;

		armxor_ck = clk_get(NULL, "armxor_ck");
		if (IS_ERR(armxor_ck))
			dev_warn(dev->dev, "Could not get armxor_ck\n");
		else {
			fclk_rate = clk_get_rate(armxor_ck);
			clk_put(armxor_ck);
		}
		/* TRM for 5912 says the I2C clock must be prescaled to be
		 * between 7 - 12 MHz. The XOR input clock is typically
		 * 12, 13 or 19.2 MHz. So we should have code that produces:
		 *
		 * XOR MHz	Divider		Prescaler
		 * 12		1		0
		 * 13		2		1
		 * 19.2		2		1
		 */
		if (fclk_rate > 12000000)
			psc = fclk_rate / 12000000;
	}

	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);

	/* Program desired operating rate */
	fclk_rate /= (psc + 1) * 1000;
	if (psc > 2)
		psc = 2;

	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
			   fclk_rate / (clock * 2) - 7 + psc);
	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
			   fclk_rate / (clock * 2) - 7 + psc);

	/* Take the I2C module out of reset: */
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);

	/* Enable interrupts */
	omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
			   (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
			    OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
			    OMAP_I2C_IE_AL));
	return 0;
}