C++ intr_establish函数代码示例

void
discoverypic_setup(bus_space_tag_t memt, bus_space_handle_t memh)
{
	struct discoverypic_ops *dsc;
	uint32_t val;

	dsc = malloc(sizeof(*dsc), M_DEVBUF, M_NOWAIT|M_ZERO);
	if (!dsc)
		panic("dsc_pic_setup: malloc(%zu) failed", sizeof(*dsc));

	dsc->dsc_memt = memt;
	dsc->dsc_memh = memh;
	dsc->dsc_pic.pic_get_irq = dsc_get_irq;
	dsc->dsc_pic.pic_enable_irq = dsc_enable_irq;
	dsc->dsc_pic.pic_reenable_irq = dsc_enable_irq;
	dsc->dsc_pic.pic_disable_irq = dsc_disable_irq;
	dsc->dsc_pic.pic_ack_irq = dsc_ack_irq;
	dsc->dsc_pic.pic_establish_irq = dsc_establish_irq;
	dsc->dsc_pic.pic_source_name = dsc_source_name;

	pic_add(&dsc->dsc_pic);
	KASSERT(dsc->dsc_pic.pic_intrbase == 0);

	pic = dscpic_setup(memt, memh);
	intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP7_0,
	    IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
	intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP15_8,
	    IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
	intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP23_16,
	    IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
	intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP31_24,
	    IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
}

void *
vbus_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle,
    int level, int flags, int (*handler)(void *), void *arg, const char *what)
{
	uint64_t sysino = INTVEC(ihandle);
	struct intrhand *ih;
	int err;

	ih = bus_intr_allocate(t0, handler, arg, ihandle, level,
	    NULL, NULL, what);
	if (ih == NULL)
		return (NULL);

	if (flags & BUS_INTR_ESTABLISH_MPSAFE)
		ih->ih_mpsafe = 1;

	intr_establish(ih->ih_pil, ih);
	ih->ih_ack = vbus_intr_ack;

	err = hv_intr_settarget(sysino, ih->ih_cpu->ci_upaid);
	if (err != H_EOK)
		return (NULL);

	/* Clear pending interrupts. */
	err = hv_intr_setstate(sysino, INTR_IDLE);
	if (err != H_EOK)
		return (NULL);

	err = hv_intr_setenabled(sysino, INTR_ENABLED);
	if (err != H_EOK)
		return (NULL);

	return (ih);
}

static void
amlogic_com_attach(device_t parent, device_t self, void *aux)
{
	struct amlogic_com_softc * const asc = device_private(self);
	struct com_softc * const sc = &asc->asc_sc;
	struct amlogicio_attach_args * const aio = aux;
	const struct amlogic_locators * const loc = &aio->aio_loc;
	bus_space_tag_t iot = aio->aio_core_a4x_bst;
	const bus_addr_t iobase = AMLOGIC_CORE_BASE + loc->loc_offset;
	bus_space_handle_t ioh;

	amlogic_com_ports |= __BIT(loc->loc_port);

	sc->sc_dev = self;
	sc->sc_frequency = AMLOGIC_UART_FREQ;
	sc->sc_type = COM_TYPE_NORMAL;

	if (com_is_console(iot, iobase, &ioh) == 0
	    && bus_space_subregion(iot, aio->aio_bsh,
		loc->loc_offset / 4, loc->loc_size, &ioh)) {
		panic(": can't map registers");
	}
	COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);

	com_attach_subr(sc);
	aprint_naive("\n");

	KASSERT(loc->loc_intr != AMLOGICIO_INTR_DEFAULT);
	asc->asc_ih = intr_establish(loc->loc_intr, IPL_SERIAL,
	    IST_EDGE | IST_MPSAFE, comintr, sc);
	if (asc->asc_ih == NULL)
		panic("%s: failed to establish interrupt %d",
		    device_xname(self), loc->loc_intr);
}

static void
obiouart_attach(device_t parent, device_t self, void *aux)
{
	struct com_obio_softc *osc = device_private(self);
	struct com_softc *sc = &osc->sc_sc;
	struct obio_attach_args *obio = aux;
	bus_space_tag_t bst;
	bus_space_handle_t bsh = 0;
	bus_addr_t iobase;

	sc->sc_dev = self;

	bst = obio->obio_bst;
	iobase = obio->obio_base + obio->obio_offset;
	sc->sc_frequency = ROCKCHIP_UART_FREQ;
	sc->sc_type = COM_TYPE_NORMAL;

	if (com_is_console(bst, iobase, &bsh) == 0 &&
	    bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
		panic(": can't map registers\n");
		return;
	}
	COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);

	com_attach_subr(sc);
	aprint_naive("\n");

	KASSERT(obio->obio_intr != OBIOCF_INTR_DEFAULT);
	osc->sc_ih = intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL,
			comintr, sc);
	if (osc->sc_ih == NULL)
		panic("%s: failed to establish interrup %d",
		    device_xname(self), obio->obio_intr);
}

void
com_eumb_attach(device_t parent, device_t self, void *aux)
{
	struct com_softc *sc = device_private(self);
	struct eumb_attach_args *eaa = aux;
	int comaddr, epicirq;
	bus_space_handle_t ioh;
	extern u_long ticks_per_sec;

	sc->sc_dev = self;
	found = 1;

	comaddr = (eaa->eumb_unit == 1) ? 0x4600 : 0x4500;
	if (comaddr == cnregs.cr_iobase)
		sc->sc_regs = cnregs;
	else {
		ioh = comaddr;
		bus_space_map(eaa->eumb_bt, comaddr, COM_NPORTS, 0, &ioh);
		COM_INIT_REGS(sc->sc_regs, eaa->eumb_bt, ioh, comaddr);
	}
	sc->sc_frequency = 4 * ticks_per_sec;
	epicirq = (eaa->eumb_unit == 1) ? 25 : 24;

	com_attach_subr(sc);
	intr_establish(epicirq + 16, IST_LEVEL, IPL_SERIAL, comintr, sc);
}

static void
awin_tve_attach(device_t parent, device_t self, void *aux)
{
	struct awin_tve_softc *sc = device_private(self);
	struct awinio_attach_args * const aio = aux;
	const struct awin_locators * const loc = &aio->aio_loc;
	prop_dictionary_t cfg = device_properties(self);
	int8_t	tcon_unit = -1;

	sc->sc_dev = self;
	sc->sc_bst = aio->aio_core_bst;
	bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
	    loc->loc_offset, loc->loc_size, &sc->sc_bsh);

	if (prop_dictionary_get_int8(cfg, "tcon_unit", &tcon_unit)) {
		sc->sc_tcon_unit = tcon_unit;
	} else {
		sc->sc_tcon_unit = 0; /* default value */
	}
	sc->sc_tcon_pll = awin_tcon_get_clk_pll(sc->sc_tcon_unit);
	switch (sc->sc_tcon_pll) {
	case 3:
		awin_pll3_enable();
		break;
	case 7:
		awin_pll7_enable();
		break;
	default:
		panic("awin_tve pll");
	}

	/* for now assume we're always at 0 */
	awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
	    AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_TVE0, 0);

	aprint_naive("\n");
	aprint_normal(": TV Encoder / VGA output\n");
	if (tcon_unit >= 0) {
		aprint_verbose_dev(self, ": using TCON%d, pll%d\n",
		    sc->sc_tcon_unit, sc->sc_tcon_pll);
	}

	sc->sc_i2c_blklen = 16;

#if 0
	sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
	    awin_tve_intr, sc);
	if (sc->sc_ih == NULL) {
		aprint_error_dev(self, "couldn't establish interrupt %d\n",
		    loc->loc_intr);
		return;
	}
	aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
#endif

	awin_tve_i2c_init(sc);

	awin_tve_enable(sc);
	awin_tve_read_edid(sc);
}

static void
gemini_com_attach(device_t parent, device_t self, void *aux)
{
	struct com_softc *sc = device_private(self);
	struct obio_attach_args *obio = aux;
	bus_space_tag_t iot;
	bus_space_handle_t ioh;
	bus_addr_t iobase;

	sc->sc_dev = self;
	iot = obio->obio_iot;
	iobase = obio->obio_addr;
	sc->sc_frequency = GEMINI_COM_FREQ;
	sc->sc_type = COM_TYPE_16550_NOERS;

	if (com_is_console(iot, iobase, &ioh) == 0 &&
	    bus_space_map(iot, iobase, obio->obio_size, 0, &ioh)) {
		panic(": can't map registers\n");
		return;
	}
	COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);

	com_attach_subr(sc);
	aprint_naive("\n");

	intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL_HIGH,
		comintr, sc);
}

void
le_sbdio_attach(device_t parent, device_t self, void *aux)
{
	struct le_sbdio_softc *lesc = device_private(self);
	struct sbdio_attach_args *sa = aux;
	struct lance_softc *sc = &lesc->sc_am7990.lsc;
	bus_dma_segment_t seg;
	int rseg;

	sc->sc_dev = self;
	lesc->sc_dmat = sa->sa_dmat;
	lesc->sc_bst  = sa->sa_bust;

	if (bus_space_map(lesc->sc_bst, sa->sa_addr1, 8 /* XXX */,
	    BUS_SPACE_MAP_LINEAR, &lesc->sc_bsh) != 0) {
		aprint_error(": cannot map registers\n");
		return;
	}

	/* Allocate DMA memory for the chip. */
	if (bus_dmamem_alloc(lesc->sc_dmat, LE_MEMSIZE, 0, 0, &seg, 1, &rseg,
	    BUS_DMA_NOWAIT) != 0) {
		aprint_error(": can't allocate DMA memory\n");
		return;
	}
	if (bus_dmamem_map(lesc->sc_dmat, &seg, rseg, LE_MEMSIZE,
	    (void **)&sc->sc_mem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) != 0) {
		aprint_error(": can't map DMA memory\n");
		return;
	}
	if (bus_dmamap_create(lesc->sc_dmat, LE_MEMSIZE, 1, LE_MEMSIZE,
	    0, BUS_DMA_NOWAIT, &lesc->sc_dmamap) != 0) {
		aprint_error(": can't create DMA map\n");
		return;
	}
	if (bus_dmamap_load(lesc->sc_dmat, lesc->sc_dmamap, sc->sc_mem,
	    LE_MEMSIZE, NULL, BUS_DMA_NOWAIT) != 0) {
		aprint_error(": can't load DMA map\n");
		return;
	}

	sc->sc_memsize = LE_MEMSIZE;
	sc->sc_addr = lesc->sc_dmamap->dm_segs[0].ds_addr;
	sc->sc_conf3 = LE_C3_BSWP | LE_C3_BCON;
	(*platform.ether_addr)(sc->sc_enaddr);

	sc->sc_copytodesc = lance_copytobuf_contig;
	sc->sc_copyfromdesc = lance_copyfrombuf_contig;
	sc->sc_copytobuf = lance_copytobuf_contig;
	sc->sc_copyfrombuf = lance_copyfrombuf_contig;
	sc->sc_zerobuf = lance_zerobuf_contig;
#ifdef LEDEBUG
	sc->sc_debug = 0xff;
#endif
	sc->sc_rdcsr = le_sbdio_rdcsr;
	sc->sc_wrcsr = le_sbdio_wrcsr;

	am7990_config(&lesc->sc_am7990);
	intr_establish(sa->sa_irq, am7990_intr, sc);
}

void *
pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
    int (*func)(void *), void *arg)
{
	int type;

	if (brdtype == BRD_STORCENTER && ih == 1) {
		/*
		 * XXX This is a workaround for the VT6410 IDE controller!
		 * Apparently its interrupt cannot be disabled and remains
		 * asserted during the whole device probing procedure,
		 * causing an interrupt storm.
		 * Using an edge-trigger fixes that and triggers the
		 * interrupt only once during probing.
		 */
		 type = IST_EDGE;
	} else
		type = IST_LEVEL;
	
	/*
	 * ih is the value assigned in pci_intr_map(), above.
	 * It's the EPIC IRQ #.
	 */
	return intr_establish(ih + I8259_ICU, type, level, func, arg);
}

void
hil_intio_attach(struct device *parent, struct device *self, void *aux)
{
	struct hil_softc *sc = (void *)self;
	struct intio_attach_args *ia = aux;
	extern struct consdev wsdisplay_cons;

	sc->sc_bst = ia->ia_tag;
	if (bus_space_map(sc->sc_bst, HILADDR,
	    HILMAPSIZE, 0, &sc->sc_bsh) != 0) {
		printf(": couldn't map hil controller\n");
		return;
	}

	/*
	 * Check that the configured console device is a wsdisplay.
	 */
	if (cn_tab != &wsdisplay_cons)
		hil_is_console = 0;

	hil_isr.isr_func = hil_intr;
	hil_isr.isr_arg = sc;
	hil_isr.isr_ipl = 1;
	hil_isr.isr_priority = IPL_TTY;

	printf(" ipl %d", hil_isr.isr_ipl);

	hil_attach(sc, &hil_is_console);
	intr_establish(&hil_isr, self->dv_xname);

	startuphook_establish(hil_attach_deferred, sc);
}

void
com_cpc_attach(struct device *parent, struct device *self, void *aux)
{
	struct cpcbus_attach_args *caa = aux;
	struct com_cpc_softc *sc = (struct com_cpc_softc *)self;
	int iobase = caa->cpca_addr;
	int irq = caa->cpca_irq;

	sc->sc_com.sc_iot = caa->cpca_tag;
	sc->sc_com.sc_iobase = iobase;

	if (!com_is_console(sc->sc_com.sc_iot, iobase, &sc->sc_com.sc_ioh) &&
	    bus_space_map(sc->sc_com.sc_iot, iobase, COM_NPORTS, 0,
			  &sc->sc_com.sc_ioh)) {
		printf("%s: can't map i/o space\n", self->dv_xname);
		return;
	}

	sc->sc_com.sc_frequency = CPC_COM_SPEED(caa->cpca_freq);

	com_attach_subr(&sc->sc_com);

	sc->sc_ih = intr_establish(irq, IST_LEVEL, IPL_SERIAL, comintr,
				   &sc->sc_com);
}

void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
    int (*func)(void *), void *arg, char *what)
{
	int pin, irq;
	struct pic *pic;

	pic = &i8259_pic;
	pin = irq = ih;

#if NIOAPIC > 0
	if (ih & APIC_INT_VIA_APIC) {
		pic = (struct pic *)ioapic_find(APIC_IRQ_APIC(ih));
		if (pic == NULL) {
			printf("pci_intr_establish: bad ioapic %d\n",
			    APIC_IRQ_APIC(ih));
			return NULL;
		}
		pin = APIC_IRQ_PIN(ih);
		irq = APIC_IRQ_LEGACY_IRQ(ih);
		if (irq < 0 || irq >= NUM_LEGACY_IRQS)
			irq = -1;
	}
#endif

	return intr_establish(irq, pic, pin, IST_LEVEL, level, func, arg, what);
}

static void
awin_otg_attach(device_t parent, device_t self, void *aux)
{
	struct awin_otg_softc *sc = device_private(self);
	struct awinio_attach_args * const aio = aux;
	const struct awin_locators * const loc = &aio->aio_loc;

	aprint_naive("\n");
	aprint_normal(": OTG\n");

	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
		    AWIN_USB_CLK_REG,
		    AWIN_A31_USB_CLK_USBPHY0_ENABLE |
		    AWIN_A31_USB_CLK_PHY0_ENABLE, 0);
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
		    AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_USB0, 0);
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
		    AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_USBOTG_RST, 0);
	} else {
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
		    AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_USB0, 0);
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
		    AWIN_USB_CLK_REG,
		    AWIN_USB_CLK_USBPHY_ENABLE|AWIN_USB_CLK_PHY0_ENABLE, 0);
		awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
		    AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
		    __SHIFTIN(AWIN_SRAM_CTL1_SRAMD_MAP_USB0,
			      AWIN_SRAM_CTL1_SRAMD_MAP),
		    0);
	}

	sc->sc_motg.sc_dev = self;
	sc->sc_motg.sc_bus.dmatag = aio->aio_dmat;
	sc->sc_motg.sc_iot = aio->aio_core_bst;
	bus_space_subregion(sc->sc_motg.sc_iot, aio->aio_core_bsh,
	    loc->loc_offset, loc->loc_size, &sc->sc_motg.sc_ioh);
	sc->sc_motg.sc_size = loc->loc_size;
	sc->sc_motg.sc_intr_poll = awin_otg_poll;
	sc->sc_motg.sc_intr_poll_arg = sc;

	sc->sc_motg.sc_mode = MOTG_MODE_HOST;
	sc->sc_motg.sc_ep_max = 5;
	sc->sc_motg.sc_ep_fifosize = 512;

	sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
	    awin_otg_intr, sc);
	if (sc->sc_ih == NULL) {
		aprint_error_dev(self, "couldn't establish interrupt %d\n",
		    loc->loc_intr);
		return;
	}
	device_printf(self, "interrupting at irq %d\n", loc->loc_intr);

	awin_otg_init(sc);

	motg_init(&sc->sc_motg);
}

void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
		   int (*func)(void *), void *arg)
{

	if (ih == 0 || ih >= ICU_LEN)
		panic("pci_intr_establish: bogus handle 0x%x\n", ih);

	return intr_establish(ih, IST_LEVEL, level, func, arg);
}

void
ti_sbus_attach(struct device *parent, struct device *self, void *aux)
{
	struct confargs *ca = aux;
	struct ti_sbus_softc *tsc = (void *)self;
	struct ti_softc *sc = &tsc->tsc_sc;
	bus_space_handle_t ioh;

	/* Pass on the bus tags */
	tsc->tsc_rr = ca->ca_ra.ra_reg[1];
	sc->ti_btag = &tsc->tsc_rr;
	sc->sc_dmatag = iommu_dmatag;

	if (ca->ca_ra.ra_nintr < 1) {
                printf(": no interrupt\n");
                return;
        }

	if (ca->ca_ra.ra_nreg < 2) {
                printf(": only %d register sets\n", ca->ca_ra.ra_nreg);
		return;
	}

	if (bus_space_map(&ca->ca_ra.ra_reg[1], 0,
	    ca->ca_ra.ra_reg[1].rr_len, 0, &sc->ti_bhandle)) {
		printf(": can't map registers\n");
		return;
	}

	if (bus_space_map(&ca->ca_ra.ra_reg[0], 0,
	    ca->ca_ra.ra_reg[0].rr_len, 0, &ioh)) {
		printf(": can't map registers\n");
		goto fail;
	}

	tsc->tsc_ih.ih_fun = ti_intr;
	tsc->tsc_ih.ih_arg = sc;
	intr_establish(ca->ca_ra.ra_intr[0].int_pri, &tsc->tsc_ih,
	    IPL_NET, self->dv_xname);

	bus_space_write_4(sc->ti_btag, ioh, TI_PCI_CMDSTAT, 0x02000006);
	bus_space_write_4(sc->ti_btag, ioh, TI_PCI_BIST, 0xffffffff);
	bus_space_write_4(sc->ti_btag, ioh, TI_PCI_LOMEM, 0x00000400);

	bus_space_unmap(&ca->ca_ra.ra_reg[0], ioh, ca->ca_ra.ra_reg[0].rr_len);

	sc->ti_sbus = 1;
	if (ti_attach(sc) == 0)
		return;

fail:
	bus_space_unmap(&ca->ca_ra.ra_reg[1], sc->ti_bhandle,
	    ca->ca_ra.ra_reg[1].rr_len);
}