C++ icache_enable函数代码示例

void enable_caches(void)
{
	icache_enable();
#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
#endif
}

int board_init( void )
{
	DECLARE_GLOBAL_DATA_PTR;

	/* Active BBUS modules */
	*get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;

#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new
	/* arch number of OMAP 1510-Board */
	/* to be changed for OMAP 1610 Board */
	gd->bd->bi_arch_number = 234;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x10000100;


/* this speeds up your boot a quite a bit.  However to make it
 *  work, you need make sure your kernel startup flush bug is fixed.
 *  ... rkw ...
 */
	icache_enable();

	flash__init();
	ether__init();
	return 0;
}

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	long psize;
#ifndef CONFIG_SYS_RAMBOOT
	long sizelittle, sizebig;
#endif

	memctl->memc_psrt = CONFIG_SYS_PSRT;
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

#ifndef CONFIG_SYS_RAMBOOT
	/* 60x SDRAM setup:
	 */
	sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
						  (uchar *) CONFIG_SYS_SDRAM_BASE);
	sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
						  (uchar *) CONFIG_SYS_SDRAM_BASE);
	if (sizelittle < sizebig) {
		psize = sizebig;
	} else {
		psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
						  (uchar *) CONFIG_SYS_SDRAM_BASE);
	}
#endif /* CONFIG_SYS_RAMBOOT */

	icache_enable ();

	return (psize);
}

int spr_post_test (int flags)
{
	int ret = 0;
	int ic = icache_status ();
	int i;

	unsigned long code[] = {
		0x7c6002a6,				/* mfspr r3,SPR */
		0x4e800020				/* blr          */
	};
	unsigned long (*get_spr) (void) = (void *) code;

	if (ic)
		icache_disable ();

	for (i = 0; i < spr_test_list_size; i++) {
		int num = spr_test_list[i].number;

		/* mfspr r3,num */
		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);

		if ((get_spr () & spr_test_list[i].mask) !=
			(spr_test_list[i].value & spr_test_list[i].mask)) {
			post_log ("The value of %s special register "
				  "is incorrect: 0x%08X\n",
					spr_test_list[i].name, get_spr ());
			ret = -1;
		}
	}

	if (ic)
		icache_enable ();

	return ret;
}

int board_init (void)
{
	volatile unsigned int tmp = 0;
	DECLARE_GLOBAL_DATA_PTR;


	gd->bd->bi_arch_number = MACH_TYPE_NS115_PAD_REF;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x80000100;

//	gd->flags = 0;

	icache_enable ();
	rvpb_timer_init();
	
	
	writel(0x1,0x05042c00);
	writel(0x10000000,0x05042c04);
	//set lcd pinmux 
	writel(0x0,0x05822004);    
	writel(0x01000000,0x05822008);


#ifdef CONFIG_FASTBOOT_RECOVERY

	unsigned int hdmi_soft_update;
	hdmi_soft_update = nufront_get_gpio_value(26);	
	if(hdmi_soft_update == 0x0){
		fastboot_flag = 1;
	}
#endif 
	return 0;
}

int board_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	u32 reg;

	dm9000_pre_init();

	/* set GPIO for Display Controller */
	reg = readl(MIFPCON);
	reg &= ~(1 << 3);
	writel(reg, MIFPCON);

	reg = readl(SPCON);
	reg &= ~(3 << 0);
	writel(reg | 0x1, SPCON);

	writel(0xaaaaaaaa, GPICON);
	writel(0xaaaaaa, GPJCON);

	gd->bd->bi_arch_number = MACH_TYPE;
	gd->bd->bi_boot_params = (PHYS_SDRAM_1+0x100);

#if 0
	icache_enable();
	dcache_enable();
#endif
	return 0;
}

uint32_t
cpudep_ap_bootstrap()
{
	uint32_t msr, sp, csr;

	/* Enable L1 caches */
	csr = mfspr(SPR_L1CSR0);
	if ((csr & L1CSR0_DCE) == 0) {
		dcache_inval();
		dcache_enable();
	}

	csr = mfspr(SPR_L1CSR1);
	if ((csr & L1CSR1_ICE) == 0) {
		icache_inval();
		icache_enable();
	}

	/* Set MSR */
	msr = PSL_ME;
	mtmsr(msr);

	/* Assign pcpu fields, return ptr to this AP's idle thread kstack */
	pcpup->pc_curthread = pcpup->pc_idlethread;
	pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
	sp = pcpup->pc_curpcb->pcb_sp;

	/* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */

	return (sp);
}

int arch_cpu_init(void)
{
	icache_enable();
	__asm_invalidate_dcache_all();
	__asm_invalidate_tlb_all();
	return 0;
}

int board_init(void)
{
	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;

	icache_enable();

#ifdef USE_920T_MMU
	dcache_enable();
#endif

	/*
	 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
	 * 14.7456/2 MHz
	 */
	uint32_t value = readl(&syscon->pwrcnt);
	value |= SYSCON_PWRCNT_UART_BAUD;
	writel(value, &syscon->pwrcnt);

	/* Enable the uart in devicecfg */
	value = readl(&syscon->devicecfg);
	value |= 1<<18 /* U1EN */;
	writel(0xAA, &syscon->sysswlock);
	writel(value, &syscon->devicecfg);

	/* Machine number, as defined in linux/arch/arm/tools/mach-types */
	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;

	/* We have a console */
	gd->have_console = 1;

	return 0;
}

int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	switch (argc) {
	case 2:			/* on / off	*/
		switch (on_off(argv[1])) {
#if 0	/* prevented by varargs handling; FALLTROUGH is harmless, too */
		default: printf ("Usage:\n%s\n", cmdtp->usage);
			return;
#endif
		case 0:	icache_disable();
			break;
		case 1:	icache_enable ();
			break;
		}
		/* FALL TROUGH */
	case 1:			/* get status */
		printf ("Instruction Cache is %s\n",
			icache_status() ? "ON" : "OFF");
		return 0;
	default:
		printf ("Usage:\n%s\n", cmdtp->usage);
		return 1;
	}
	return 0;
}

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/*
	 * if we come from RAM we assume the CPU is
	 * already initialized.
	 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);

	/* Kill watchdog so we can initialize the PLL */
	wdog_reg->wcr = 0;

	/* FlexBus Chipselect */
	init_fbcs();
#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */

#ifdef CONFIG_FSL_I2C
	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif

	/* enable instruction cache now */
	icache_enable();
}

int arch_cpu_init(void)
{
	struct pxa1978accu_registers *accu =
		(struct pxa1978accu_registers *)PXA1978_ACCU_BASE;

	writel(UARTCLK14745KHZ, &accu->uart1);

	/* Set timer clock CONFIG_SYS_HZ_CLOCK = 26MHz */
	writel(TIMERCLK_26MHZ, &accu->timer1);

#ifdef CONFIG_I2C_MV
	/* Enable I2C clock */
	/* TODO */
#endif

#ifdef CONFIG_MMP_DISP
	/* TODO */
#endif

#ifdef CONFIG_MV_SDHCI
	/* Enable mmc clock */
	/* TODO */
#endif

#ifdef CONFIG_MV_UDC
	/* Enable usb clock */
	/* TODO */
#endif

	icache_enable();

	return 0;
}

int board_init(void)
{
	/* temporary hack to clear pending irqs before Linux as it 
	   will hang Linux */

	XIo_Out32(0xe0001014, 0x26d);

	/* temporary hack to take USB out of reset til the is fixed
	   in Linux */

	XIo_Out32(0xe000a204, 0x80);
	XIo_Out32(0xe000a208, 0x80);
	XIo_Out32(0xe000a040, 0x80);
	XIo_Out32(0xe000a040, 0x00);
	XIo_Out32(0xe000a040, 0x80);

	icache_enable();

#ifdef CONFIG_FPGA
	fpga_init();
	fpga_add(fpga_xilinx, &fpga);
#endif

	return 0;
}

int board_init (void)
{
	if (machine_is_omap_h2())
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
	else if (machine_is_omap_innovator())
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
	else
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x10000100;

	/* Configure MUX settings */
	set_muxconf_regs ();
	peripheral_power_enable ();

/* this speeds up your boot a quite a bit.  However to make it
 *  work, you need make sure your kernel startup flush bug is fixed.
 *  ... rkw ...
 */
	icache_enable ();

	flash__init ();
	ether__init ();
	return 0;
}

/*
 * Set up the memory map and initialize registers
 */
void cpu_init_f(void)
{
	sim_t *sim = (sim_t *)(MMAP_SIM);

	out_8(&sim->sypcr, 0x00);
	out_8(&sim->swivr, 0x0f);
	out_8(&sim->swsr,  0x00);
	out_8(&sim->mpark, 0x00);

	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);

	/* timer 2 not masked */
	out_be32(&icr->imr, 0xfffffbff);

	out_8(&icr->icr0, 0x00); /* sw watchdog */
	out_8(&icr->icr1, 0x00); /* timer 1     */
	out_8(&icr->icr2, 0x88); /* timer 2     */
	out_8(&icr->icr3, 0x00); /* i2c         */
	out_8(&icr->icr4, 0x00); /* uart 0      */
	out_8(&icr->icr5, 0x00); /* uart 1      */
	out_8(&icr->icr6, 0x00); /* dma  0      */
	out_8(&icr->icr7, 0x00); /* dma  1      */
	out_8(&icr->icr8, 0x00); /* dma  2      */
	out_8(&icr->icr9, 0x00); /* dma  3      */

	/* Chipselect Init */
	init_csm();

	/* enable data/instruction cache now */
	icache_enable();
}