C++ i2c_writel函数代码示例

static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
{
        struct rk30_i2c *i2c = dev_id;
        unsigned int ipd;

        spin_lock(&i2c->lock);
        ipd = i2c_readl(i2c->regs + I2C_IPD);
        if(i2c->state == STATE_IDLE){
                dev_info(i2c->dev, "Addr[0x%02x]  irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
                i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
                goto out;
        }

#if defined(CONFIG_MFD_TRS65910)	//for trs65910 Trsilicon peter
	if(ipd & I2C_NAKRCVIPD && i2c->addr == 0x2d){
		i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
		goto out;
	}else  if(ipd & I2C_NAKRCVIPD){
		i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
		i2c->error = -EAGAIN;
		goto out;
	}
#else
	if(ipd & I2C_NAKRCVIPD){
		i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
		i2c->error = -EAGAIN;
		goto out;
	}
#endif
        rk30_i2c_irq_nextblock(i2c, ipd);
out:
        spin_unlock(&i2c->lock);
        return IRQ_HANDLED;
}

static void rk30_irq_write_prepare(struct rk30_i2c *i2c)
{
    unsigned int data = 0, cnt = 0, i, j;
    unsigned char byte;

    if(is_msgend(i2c)) {
        rk30_i2c_stop(i2c, i2c->error);
        return;
    }
    for(i = 0; i < 8; i++) {
        data = 0;
        for(j = 0; j < 4; j++) {
            if(is_msgend(i2c))
                break;
            if(i2c->msg_ptr == 0 && cnt == 0)
                byte = (i2c->addr & 0x7f) << 1;
            else
                byte =  i2c->msg->buf[i2c->msg_ptr++];
            cnt++;
            data |= (byte << (j * 8));
        }
        i2c_writel(data, i2c->regs + I2C_TXDATA_BASE + 4 * i);
        if(is_msgend(i2c))
            break;
    }
    i2c_writel(cnt, i2c->regs + I2C_MTXCNT);
}

static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
{
	/* Will force clear all statuses */
	i2c_writel(0x7C, i2c->reg_base + LPC24XX_I2CONCLR);
	i2c_writel(0, i2c->reg_base + LPC24XX_I2ADDR);
	i2c_writel(LPC24XX_I2EN, i2c->reg_base + LPC24XX_I2CONSET);
}

static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
{
	unsigned long timeout = jiffies + HZ;
	unsigned int offset;
	u32 mask, val;

	if (i2c_dev->hw->has_mst_fifo) {
		mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
		       I2C_MST_FIFO_CONTROL_RX_FLUSH;
		offset = I2C_MST_FIFO_CONTROL;
	} else {
		mask = I2C_FIFO_CONTROL_TX_FLUSH |
		       I2C_FIFO_CONTROL_RX_FLUSH;
		offset = I2C_FIFO_CONTROL;
	}

	val = i2c_readl(i2c_dev, offset);
	val |= mask;
	i2c_writel(i2c_dev, val, offset);

	while (i2c_readl(i2c_dev, offset) & mask) {
		if (time_after(jiffies, timeout)) {
			dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
			return -ETIMEDOUT;
		}
		msleep(1);
	}
	return 0;
}

static inline void rk30_i2c_clean_stop(struct rk30_i2c *i2c)
{
    unsigned int con = i2c_readl(i2c->regs + I2C_CON);

    con &= ~I2C_CON_STOP;
    i2c_writel(con, i2c->regs + I2C_CON);
}

static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
{
	u32 int_mask;

	int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
}

static inline void rk30_i2c_send_stop(struct rk30_i2c *i2c)
{
    unsigned int con = i2c_readl(i2c->regs + I2C_CON);

    con |= I2C_CON_STOP;
    if(con & I2C_CON_START)
        dev_warn(i2c->dev, "I2C_CON: start bit is set\n");

    i2c_writel(con, i2c->regs + I2C_CON);
}

static inline void rk30_set_rx_mode(struct rk30_i2c *i2c, unsigned int lastnak)
{
    unsigned long con = i2c_readl(i2c->regs + I2C_CON);

    con &= (~I2C_CON_MASK);
    con |= (I2C_CON_MOD_RX << 1);
    if(lastnak)
        con |= I2C_CON_LASTACK;
    i2c_writel(con, i2c->regs + I2C_CON);
}

static inline void rk30_i2c_enable(struct rk30_i2c *i2c, unsigned int lastnak)
{
    unsigned int con = 0;

    con |= I2C_CON_EN;
    con |= I2C_CON_MOD(i2c->mode);
    if(lastnak)
        con |= I2C_CON_LASTACK;
    con |= I2C_CON_START;
    i2c_writel(con, i2c->regs + I2C_CON);
}

static irqreturn_t rk30_i2c_irq(int irq, void *dev_id)
{
    struct rk30_i2c *i2c = dev_id;
    unsigned int ipd;

    spin_lock(&i2c->lock);
    ipd = i2c_readl(i2c->regs + I2C_IPD);
    if(i2c->state == STATE_IDLE) {
        dev_info(i2c->dev, "Addr[0x%02x]  irq in STATE_IDLE, ipd = 0x%x\n", i2c->addr, ipd);
        i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
        goto out;
    }

    if(ipd & I2C_NAKRCVIPD) {
        i2c_writel(I2C_NAKRCVIPD, i2c->regs + I2C_IPD);
        i2c->error = -EAGAIN;
        goto out;
    }
    rk30_i2c_irq_nextblock(i2c, ipd);
out:
    spin_unlock(&i2c->lock);
    return IRQ_HANDLED;
}

/* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
 * SCL = i2c_rate/ SCLK Divisor
*/
static void  rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
{
    unsigned long i2c_rate = clk_get_rate(i2c->clk);

    unsigned int div, divl, divh;

    if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
        return;
    i2c->i2c_rate = i2c_rate;
    i2c->scl_rate = scl_rate;
    div = rk30_ceil(i2c_rate, scl_rate * 8);
    divh = divl = rk30_ceil(div, 2);
    i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
    i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
    return;
}

static void rk30_i2c_stop(struct rk30_i2c *i2c, int ret)
{

    i2c->msg_ptr = 0;
    i2c->msg = NULL;
    if(ret == -EAGAIN) {
        i2c->state = STATE_IDLE;
        i2c->is_busy = 0;
        wake_up(&i2c->wait);
        return;
    }
    i2c->error = ret;
    i2c_writel(I2C_STOPIEN, i2c->regs + I2C_IEN);
    i2c->state = STATE_STOP;
    rk30_i2c_send_stop(i2c);
    return;
}

static void rk30_irq_read_prepare(struct rk30_i2c *i2c)
{
    unsigned int cnt, len = i2c->msg->len - i2c->msg_ptr;

    if(len <= 32 && i2c->msg_ptr != 0)
        rk30_set_rx_mode(i2c, 1);
    else if(i2c->msg_ptr != 0)
        rk30_set_rx_mode(i2c, 0);

    if(is_msgend(i2c)) {
        rk30_i2c_stop(i2c, i2c->error);
        return;
    }
    if(len > 32)
        cnt = 32;
    else
        cnt = len;
    i2c_writel(cnt, i2c->regs + I2C_MRXCNT);
}

static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
{
	long timeout = jiffies + HZ;
	int ret = 0;

	/*
	 * If the transfer needs to abort for some reason, we'll try to
	 * force a stop condition to clear any pending bus conditions
	 */
	i2c_writel(LPC24XX_STO, i2c->reg_base + LPC24XX_I2CONSET);

	/* Wait for status change */
	while (jiffies < timeout &&
		(i2c_readl(i2c->reg_base + LPC24XX_I2STAT) != m_i2c_idle))
		cpu_relax();

	if (i2c_readl(i2c->reg_base + LPC24XX_I2STAT) != m_i2c_idle) {
		/* Bus was not idle, try to reset adapter */
		i2c_lpc2k_reset(i2c);
		ret = -EBUSY;
	}

	return ret;
}

/* rk30_i2c_doxfer
 *
 * this starts an i2c transfer
*/
static int rk30_i2c_doxfer(struct rk30_i2c *i2c,
                           struct i2c_msg *msgs, int num)
{
    unsigned long timeout, flags;
    int error = 0;
    /* 32 -- max transfer bytes
     * 2 -- addr bytes * 2
     * 3 -- max reg addr bytes
     * 9 -- cycles per bytes
     * max cycles: (32 + 2 + 3) * 9 --> 400 cycles
     */
    int msleep_time = 400 * 1000/ i2c->scl_rate; // ms

    if (i2c->suspended) {
        dev_err(i2c->dev, "i2c is suspended\n");
        return -EIO;
    }

    spin_lock_irqsave(&i2c->lock, flags);
    if(rk30_i2c_set_master(i2c, msgs, num) < 0) {
        spin_unlock_irqrestore(&i2c->lock, flags);
        dev_err(i2c->dev, "addr[0x%02x] set master error\n", msgs[0].addr);
        return -EIO;
    }
    i2c->addr = msgs[0].addr;
    i2c->msg_ptr = 0;
    i2c->error = 0;
    i2c->is_busy = 1;
    i2c->state = STATE_START;
    i2c->complete_what = 0;
    i2c_writel(I2C_STARTIEN, i2c->regs + I2C_IEN);
    spin_unlock_irqrestore(&i2c->lock, flags);

    rk30_i2c_enable(i2c, (i2c->count > 32)?0:1); //if count > 32,  byte(32) send ack

    if (in_atomic()) {
        int tmo = I2C_WAIT_TIMEOUT * USEC_PER_MSEC;
        while(tmo-- && i2c->is_busy != 0)
            udelay(1);
        timeout = (tmo <= 0)?0:1;
    } else
        timeout = wait_event_timeout(i2c->wait, (i2c->is_busy == 0), msecs_to_jiffies(I2C_WAIT_TIMEOUT));

    spin_lock_irqsave(&i2c->lock, flags);
    i2c->state = STATE_IDLE;
    error = i2c->error;
    spin_unlock_irqrestore(&i2c->lock, flags);

    if (timeout == 0) {
        if(error < 0)
            i2c_dbg(i2c->dev, "error = %d\n", error);
        else if((i2c->complete_what !=COMPLETE_READ  && i2c->complete_what != COMPLETE_WRITE)) {
            dev_err(i2c->dev, "Addr[0x%02x] wait event timeout, state: %d, is_busy: %d, error: %d, complete_what: 0x%x, ipd: 0x%x\n",
                    msgs[0].addr, i2c->state, i2c->is_busy, error, i2c->complete_what, i2c_readl(i2c->regs + I2C_IPD));
            //rk30_show_regs(i2c);
            error = -ETIMEDOUT;
            msleep(msleep_time);
            rk30_i2c_send_stop(i2c);
            msleep(1);
        }
        else
            i2c_dbg(i2c->dev, "Addr[0x%02x] wait event timeout, but transfer complete\n", i2c->addr);
    }
    i2c_writel(I2C_IPD_ALL_CLEAN, i2c->regs + I2C_IPD);
    rk30_i2c_disable_irq(i2c);
    rk30_i2c_disable(i2c);

    if(error == -EAGAIN)
        i2c_dbg(i2c->dev, "No ack(complete_what: 0x%x), Maybe slave(addr: 0x%02x) not exist or abnormal power-on\n",
                i2c->complete_what, i2c->addr);
    return error;
}