C++ enable_smbus函数代码示例

void main(unsigned long bist)
{
	int s3resume = 0;

	if (bist == 0)
		enable_lapic();

	/* Force PCIRST# */
	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
	udelay(200 * 1000);
	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);

	ich7_enable_lpc();
	early_superio_config();

	/* Set up the console */
	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	if (MCHBAR16(SSKPD) == 0xCAFE) {
		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
		outb(0x6, 0xcf9);
		halt();
	}

	/* Perform some early chipset initialization required
	 * before RAM initialization can work
	 */
	i945_early_initialization();

	/* This has to happen after i945_early_initialization() */
	init_artec_dongle();

	s3resume = southbridge_detect_s3_resume();

	/* Enable SPD ROMs and DDR-II DRAM */
	enable_smbus();

#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
	dump_spd_registers();
#endif

	sdram_initialize(s3resume ? 2 : 0, NULL);

	/* Perform some initialization that must run before stage2 */
	early_ich7_init();

	/* This should probably go away. Until now it is required
	 * and mainboard specific
	 */
	rcba_config();

	/* Chipset Errata! */
	fixup_i945_errata();

	/* Initialize the internal PCIe links before we go into stage2 */
	i945_late_initialization(s3resume);
}

static void main(unsigned long bist)
{
	unsigned long x;
	device_t dev;

	/* Enable multifunction for northbridge. */
	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);

	w83697hf_set_clksel_48(DUMMY_DEV);
	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();

	enable_smbus();
	smbus_fixup(&ctrl);

	/* Halt if there was a built-in self test failure. */
	report_bist_failure(bist);

	print_debug("Enabling mainboard devices\n");
	enable_mainboard_devices();

	print_debug("Enable F-ROM Shadow RAM\n");
	enable_shadow_ram();

	print_debug("Setup CPU Interface\n");
	c3_cpu_setup(ctrl.d0f2);

	ddr_ram_setup();

	if (bist == 0)
		early_mtrr_init();
}

void main(unsigned long bist)
{
	if (bist == 0) {
#if 0
		enable_lapic();
		init_timer();
#endif
	}

	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

#if 0
	print_pci_devices();
#endif

	if (!bios_reset_detected()) {
        	enable_smbus();
#if 0
		dump_spd_registers();
		dump_smbus_registers();
#endif
		sdram_set_registers();
		sdram_set_spd_registers();
		sdram_enable();
	}

#if 0
	dump_pci_devices();
	dump_pci_device(PCI_DEV(0, 0, 0));
#endif
}

void main(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);

	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

	/* setup PCIe MMCONF base address */
	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
			   CONFIG_MMCONF_BASE_ADDRESS >> 16);

        smbus_write_byte(0x6f, 0x00, 0x63);
        smbus_write_byte(0x6f, 0x01, 0x04);
        smbus_write_byte(0x6f, 0x02, 0x53);
        smbus_write_byte(0x6f, 0x03, 0x39);
        smbus_write_byte(0x6f, 0x08, 0x06);
        smbus_write_byte(0x6f, 0x09, 0x00);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}

/**
 * Setup mainboard specific registers pre raminit.
 */
static void mb_early_setup(void)
{
	/* - Hub Interface to PCI Bridge Registers - */
	/* 12-Clock Retry Enable */
	pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
	/* Master Latency Timer Count */
	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
	/* I/O Address Base */
	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);

	/* - LPC Interface Bridge Registers - */
	/* Delayed Transaction Enable */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
	/* Disable the TCO Timer system reboot feature */
	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
	/* CPU Frequency Strap */
	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
	/* ACPI base address and enable Resource Indicator */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
	/* Enable the SMBUS */
	enable_smbus();
	/* ACPI base address and disable Resource Indicator */
	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
	/*  ACPI Enable */
	pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}

void mainboard_romstage_entry(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);

	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

        smbus_write_byte(0x6f, 0x00, 0x63);
        smbus_write_byte(0x6f, 0x01, 0x04);
        smbus_write_byte(0x6f, 0x02, 0x53);
        smbus_write_byte(0x6f, 0x03, 0x39);
        smbus_write_byte(0x6f, 0x08, 0x06);
        smbus_write_byte(0x6f, 0x09, 0x00);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}

void mainboard_romstage_entry(unsigned long bist)
{
	const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };

	if (bist == 0)
		enable_lapic();

	/* Disable watchdog timer */
	RCBA32(0x3410) = RCBA32(0x3410) | 0x20;

	/* Set southbridge and Super I/O GPIOs. */
	mb_gpio_init();

	nm10_enable_lpc();
	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();

	report_bist_failure(bist);
	enable_smbus();

	pineview_early_initialization();

	post_code(0x30);

	printk(BIOS_DEBUG, "Initializing memory\n");
	sdram_initialize(0, spd_addrmap);
	printk(BIOS_DEBUG, "Memory initialized\n");

	post_code(0x31);
	ram_check(0x200000,0x300000);

	rcba_config();
}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
	static const uint16_t spd_addr [] = {
		DIMM0, DIMM2, 0, 0,
		DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
		DIMM4, DIMM6, 0, 0,
		DIMM5, DIMM7, 0, 0,
#endif
	};

	int needs_reset;
	unsigned bsp_apicid = 0, nodes;
	struct mem_controller ctrl[8];

	if (bist == 0)
		bsp_apicid = init_cpus(cpu_init_detectedx);

	pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	setup_default_resource_map();

	needs_reset = setup_coherent_ht_domain();

#if CONFIG_LOGICAL_CPUS
	// It is said that we should start core1 after all core0 launched
	start_other_cores();
	wait_all_other_cores_started(bsp_apicid);
#endif
	/* This is needed to be able to call udelay().  It could be moved to
	 * memreset_setup, since udelay is called in memreset. */
	init_timer();

	// automatically set that for you, but you might meet tight space
	needs_reset |= ht_setup_chains_x();

       	if (needs_reset) {
	       	print_info("ht reset -\n");
	       	soft_reset();
       	}

	allow_all_aps_stop(bsp_apicid);

	nodes = get_nodes();

	fill_mem_ctrl(nodes, ctrl, spd_addr);

	enable_smbus();

	memreset_setup();

	sdram_initialize(nodes, ctrl);

	post_cache_as_ram();
}

void main(unsigned long bist)
{
	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	enable_smbus();
	report_bist_failure(bist);
	dump_spd_registers();
	sdram_set_registers();
	sdram_set_spd_registers();
	sdram_enable();
}

void mainboard_romstage_entry(unsigned long bist)
{
	/* TODO: It's a PC87364 actually! */
	pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	enable_smbus();
	report_bist_failure(bist);
	dump_spd_registers();
	sdram_set_registers();
	sdram_set_spd_registers();
	sdram_enable();
}

void main(unsigned long bist)
{
	int s3resume = 0, boot_mode = 0;

	if (bist == 0)
		enable_lapic();

	ich7_enable_lpc();
	/* Enable SuperIO PM */
	lpc47m15x_enable_serial(PME_DEV, 0x680);
	lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */

	/* Set up the console */
	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	if (MCHBAR16(SSKPD) == 0xCAFE) {
		printk(BIOS_DEBUG, "soft reset detected.\n");
		boot_mode = 1;
	}

	/* Perform some early chipset initialization required
	 * before RAM initialization can work
	 */
	i945_early_initialization();

	s3resume = southbridge_detect_s3_resume();

	/* Enable SPD ROMs and DDR-II DRAM */
	enable_smbus();

#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
	dump_spd_registers();
#endif

	sdram_initialize(s3resume ? 2 : boot_mode, NULL);

	/* Perform some initialization that must run before stage2 */
	early_ich7_init();

	/* This should probably go away. Until now it is required
	 * and mainboard specific
	 */
	rcba_config();

	/* Chipset Errata! */
	fixup_i945_errata();

	/* Initialize the internal PCIe links before we go into stage2 */
	i945_late_initialization(s3resume);
}

void mainboard_romstage_entry(unsigned long bist)
{
	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	report_bist_failure(bist);

	enable_smbus();
	dump_spd_registers();
	sdram_set_registers();
	sdram_set_spd_registers();
	sdram_enable();
}

void main(unsigned long bist)
{
	/* Enable multifunction for northbridge. */
	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);

	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	enable_smbus();
	smbus_fixup(&ctrl);
	report_bist_failure(bist);
	ddr_ram_setup(&ctrl);
}

void main(unsigned long bist)
{
	/* FIXME: It's a Winbond W83977EF, actually. */
	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	report_bist_failure(bist);

	enable_smbus();
	dump_spd_registers();
	sdram_set_registers();
	sdram_set_spd_registers();
	sdram_enable();
}

void main(unsigned long bist)
{
	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	report_bist_failure(bist);
	enable_smbus();
	dump_spd_registers();
	sdram_set_registers();
	sdram_set_spd_registers();
	sdram_enable();
	dump_spd_registers();
}