本文整理汇总了C++中eint_irq_to_bit函数的典型用法代码示例。如果您正苦于以下问题:C++ eint_irq_to_bit函数的具体用法?C++ eint_irq_to_bit怎么用?C++ eint_irq_to_bit使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了eint_irq_to_bit函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: s5p_irq_eint_unmask
static void s5p_irq_eint_unmask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
}
示例2: s3c_irq_eint_mask
static inline void s3c_irq_eint_mask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S3C64XX_EINT0MASK);
}
示例3: s5p_irq_eint_unmask
static void s5p_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}
示例4: s3c_irq_eint_unmask
static void s3c_irq_eint_unmask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S3C64XX_EINT0MASK);
}
示例5: s5p_irq_eint_mask
static inline void s5p_irq_eint_mask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S5P_EINTMASK(eint_mask_reg(irq)));
mask |= eint_irq_to_bit(irq);
__raw_writel(mask, S5P_EINTMASK(eint_mask_reg(irq)));
}
示例6: s3c_irq_eint_unmask
static void s3c_irq_eint_unmask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S5PC1XX_EINTMASK(eint_mask_reg(irq)));
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S5PC1XX_EINTMASK(eint_mask_reg(irq)));
}
示例7: s3c_irq_eint_ack
static inline void s3c_irq_eint_ack(unsigned int irq)
{
__raw_writel(eint_irq_to_bit(irq), S5PC11X_EINTPEND(eint_pend_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
u32 pending;
pending = __raw_readl(S5PC11X_EINTPEND(eint_pend_reg(irq)));
#endif
}
示例8: s3c_pm_clear_eint
static void s3c_pm_clear_eint(unsigned int irq)
{
u32 mask;
/*clear pending*/
mask = readl(S5PV210_EINTPEND(eint_pend_reg(irq)));
mask &= (eint_irq_to_bit(irq));
writel(mask, S5PV210_EINTPEND(eint_pend_reg(irq)));
}
示例9: exynos4_irq_eint_unmask
static void exynos4_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
spin_lock(&eint_lock);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
spin_unlock(&eint_lock);
}
示例10: s3c_irq_eint_unmask
static void s3c_irq_eint_unmask(unsigned int irq)
{
u32 mask;
mask = __raw_readl(S5PC11X_EINTMASK(eint_mask_reg(irq)));
mask &= ~(eint_irq_to_bit(irq));
__raw_writel(mask, S5PC11X_EINTMASK(eint_mask_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
mask = __raw_readl(S5PC11X_EINTMASK(eint_mask_reg(irq)));
#endif
}
示例11: s5pc11x_pm_clear_eint
static void s5pc11x_pm_clear_eint(unsigned int irq)
{
u32 mask;
/*clear pending*/
mask = readl(S5PC11X_EINTPEND(eint_pend_reg(irq)));
mask &= (eint_irq_to_bit(irq));
writel(mask, S5PC11X_EINTPEND(eint_pend_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_EINTPEND(eint_pend_reg(irq)));
#endif
}
示例12: s5p_irq_eint_unmask
static void s5p_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
/* for level triggered interrupts, masking doesn't prevent
* the interrupt from becoming pending again. by the time
* the handler (either irq or thread) can do its thing to clear
* the interrupt, it's too late because it could be pending
* already. we have to ack it here, after the handler runs,
* or else we get a false interrupt.
*/
if (irqd_is_level_type(data))
s5p_irq_eint_ack(data);
mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
mask &= ~(eint_irq_to_bit(data->irq));
__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
}
示例13: s3c64xx_init_irq_eint
static int __init s3c64xx_init_irq_eint(void)
{
int irq;
/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
if (of_have_populated_dt())
return -ENODEV;
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
set_irq_flags(irq, IRQF_VALID);
}
irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
return 0;
}
示例14: exynos4_irq_eint_ack
static inline void exynos4_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
示例15: s5pc11x_pm_set_eint
// intr_mode 0x2=>falling edge, 0x3=>rising dege, 0x4=>Both edge
static void s5pc11x_pm_set_eint(unsigned int irq, unsigned int intr_mode)
{
int offs = (irq);
int shift;
u32 ctrl, mask, tmp;
//u32 newvalue = 0x2; // Falling edge
shift = (offs & 0x7) * 4;
if((0 <= offs) && (offs < 8)) {
tmp = readl(S5PC11X_GPH0CON);
tmp |= (0xf << shift);
writel(tmp , S5PC11X_GPH0CON);
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_GPH0CON); // FIX for EVT0 bug
#endif
/*pull up disable*/
}
else if((8 <= offs) && (offs < 16)) {
tmp = readl(S5PC11X_GPH1CON);
tmp |= (0xf << shift);
writel(tmp , S5PC11X_GPH1CON);
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_GPH1CON); // FIX for EVT0 bug
#endif
}
else if((16 <= offs) && (offs < 24)) {
tmp = readl(S5PC11X_GPH2CON);
tmp |= (0xf << shift);
writel(tmp , S5PC11X_GPH2CON);
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_GPH2CON); // FIX for EVT0 bug
#endif
}
else if((24 <= offs) && (offs < 32)) {
tmp = readl(S5PC11X_GPH3CON);
tmp |= (0xf << shift);
writel(tmp , S5PC11X_GPH3CON);
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_GPH3CON); // FIX for EVT0 bug
#endif
}
else {
printk(KERN_ERR "No such irq number %d", offs);
return;
}
/*special handling for keypad eint*/
if( (24 <= irq) && (irq <= 27))
{ // disable the pull up
tmp = readl(S5PC11X_GPH3PUD);
tmp &= ~(0x3 << ((offs & 0x7) * 2));
writel(tmp, S5PC11X_GPH3PUD);
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_GPH3PUD); // FIX for EVT0 bug
#endif
DBG("S5PC11X_GPH3PUD = %x\n",readl(S5PC11X_GPH3PUD));
}
/*Set irq type*/
mask = 0x7 << shift;
ctrl = readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
ctrl &= ~mask;
//ctrl |= newvalue << shift;
ctrl |= intr_mode << shift;
writel(ctrl, S5PC11X_EINTCON(eint_conf_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
#endif
/*clear mask*/
mask = readl(S5PC11X_EINTMASK(eint_mask_reg(irq)));
mask &= ~(eint_irq_to_bit(irq));
writel(mask, S5PC11X_EINTMASK(eint_mask_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_EINTMASK(eint_mask_reg(irq)));
#endif
/*clear pending*/
mask = readl(S5PC11X_EINTPEND(eint_pend_reg(irq)));
mask &= (eint_irq_to_bit(irq));
writel(mask, S5PC11X_EINTPEND(eint_pend_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
readl(S5PC11X_EINTPEND(eint_pend_reg(irq)));
#endif
/*Enable wake up mask*/
tmp = readl(S5P_EINT_WAKEUP_MASK);
tmp &= ~(1 << (irq));
writel(tmp , S5P_EINT_WAKEUP_MASK);
DBG("S5PC11X_EINTCON = %x\n",readl(S5PC11X_EINTCON(eint_conf_reg(irq))));
DBG("S5PC11X_EINTMASK = %x\n",readl(S5PC11X_EINTMASK(eint_mask_reg(irq))));
DBG("S5PC11X_EINTPEND = %x\n",readl(S5PC11X_EINTPEND(eint_pend_reg(irq))));
return;
}