C++ eieio函数代码示例

void
cpminit(void)
{
	IMM *io;

	io = m->iomem;
	io->sdcr = 1;
	io->lccr &= ~1;	/* disable LCD */
	io->pcint = 0;	/* disable all port C interrupts */
	io->pcso = 0;
	io->pcdir =0;
	io->pcpar = 0;
	io->pcdat = 0;
	io->papar = 0;
	io->padir = 0;
	io->paodr = 0;
	io->padat = 0;
	io->pbpar = 0;
	io->pbdir = 0;
	io->pbodr = 0;
	io->pbdat = 0;
	eieio();

	for(io->cpcr = 0x8001; io->cpcr & 1;)	/* reset all CPM channels */
		eieio();

	mapinit(&bdmap, bdmapv, sizeof(bdmapv));
	mapfree(&bdmap, DPBASE, BDSIZE);
}

IOReturn Core99NVRAM::writeBlock(unsigned char *sourceAddress)
{
  long     cnt;
  IOReturn error;
  
  // Write the data byte by byte.
  for (cnt = 0; cnt < kCore99NVRAMSize; cnt++) {
    nvramNext[cnt] = kCore99NVRAMWriteSetupCmd;
    eieio();
    
    nvramNext[cnt] = sourceAddress[cnt];
    eieio();
    
    error = waitForCommandDone();
    if (error != kIOReturnSuccess) break;
  }
  
  // Write the Reset Command.
  *nvramNext = kCore99NVRAMResetDeviceCmd;
  eieio();
  
  if (error == kIOReturnSuccess) {
    error = verifyWriteBlock(sourceAddress);
  }
  
  return error;
}

void
adb_readin(void)
{
    int i, j;
    unsigned char d[64];

    if (ADB_B & 8) {
	printf("ADB_B: %x\n", ADB_B);
	return;
    }
    i = 0;
    adb_wait();
    j = ADB_SR;
    eieio();
    ADB_B &= ~0x20;
    eieio();
    for (;;) {
	if (adb_wait() < 0)
	    break;
	d[i++] = ADB_SR;
	eieio();
	if (ADB_B & 8)
	    break;
	ADB_B ^= 0x10;
	eieio();
    }
    ADB_B |= 0x30;
    if (adb_wait() == 0)
	j = ADB_SR;
    for (j = 0; j < i; ++j)
	printf("%.2x ", d[j]);
    printf("\n");
}

static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl)
{
	out_be32((void *)hwif->io_ports.ctl_addr, ctl);
	eieio();
	in_be32((void *)(hwif->dma_base + 0x01c));
	eieio();
}

static void
initialise(IICregs *iic, int intrmsk)
{
    int d;

    d = (m->opbhz-1000000)/10000000;
    if(d <= 0)
        d = 1;	/* just in case OPB freq < 20 Mhz */
    /* initialisation (see 22.4, p. 22-23) */
    iic->lmadr = 0;
    iic->hmadr = 0;
    iic->sts = Scmp|Irqa;
    iic->extsts = Irqp | Irqd | La | Ict | Xfra;
    iic->clkdiv = d;
    iic->intrmsk = 0;	/* see below */
    iic->xfrcnt = 0;
    iic->xtcntlss = Src | Srs | Swc | Sws;
    iic->mdcntl = Fsdb | Fmdb | Eubs;	/* reset; standard mode */
    iic->cntl = 0;
    eieio();
    iic->mdcntl = 0;
    eieio();
    if(intrmsk) {
        iic->intrmsk = intrmsk;
        iic->mdcntl = Eint;
    }
}

static void
cuda_start()
{
    unsigned long flags;
    struct adb_request *req;

    /* assert cuda_state == idle */
    /* get the packet to send */
    req = current_req;
    if (req == 0)
        return;
    save_flags(flags);
    cli();
    if ((via[B] & TREQ) == 0) {
        restore_flags(flags);
        return;			/* a byte is coming in from the CUDA */
    }

    /* set the shift register to shift out and send a byte */
    via[ACR] |= SR_OUT;
    eieio();
    via[SR] = req->data[0];
    eieio();
    via[B] &= ~TIP;
    cuda_state = sent_first_byte;
    restore_flags(flags);
}

static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
{
	out_be32((void *)hwif->io_ports.command_addr, cmd);
	eieio();
	in_be32((void *)(hwif->dma_base + 0x01c));
	eieio();
}

void stop_imac_ethernet(void)
{
    void *macio, *enet;
    unsigned int macio_addr[5], enet_reg[6];
    int len;
    volatile unsigned int *dbdma;

    macio = finddevice("/pci/mac-io");
    enet = finddevice("/pci/mac-io/ethernet");
    if (macio == NULL || enet == NULL)
	return;
    len = getprop(macio, "assigned-addresses", macio_addr, sizeof(macio_addr));
    if (len != sizeof(macio_addr))
	return;
    len = getprop(enet, "reg", enet_reg, sizeof(enet_reg));
    if (len != sizeof(enet_reg))
	return;
    printf("macio base %x, dma at %x & %x\n",
	   macio_addr[2], enet_reg[2], enet_reg[4]);

    /* hope this is mapped... */
    dbdma = (volatile unsigned int *) (macio_addr[2] + enet_reg[2]);
    *dbdma = 0x80;	/* clear the RUN bit */
    eieio();
    dbdma = (volatile unsigned int *) (macio_addr[2] + enet_reg[4]);
    *dbdma = 0x80;	/* clear the RUN bit */
    eieio();
}

void udbg_init_scc(struct device_node *np)
{
	u32 *reg;
	unsigned long addr;
	int i, x;

	if (np == NULL)
		np = of_find_node_by_name(NULL, "escc");
	if (np == NULL || np->parent == NULL)
		return;

	udbg_printf("found SCC...\n");
	/* Get address within mac-io ASIC */ 
	reg = (u32 *)get_property(np, "reg", NULL);
	if (reg == NULL)
		return;
	addr = reg[0];
	udbg_printf("local addr: %lx\n", addr);
	/* Get address of mac-io PCI itself */
	reg = (u32 *)get_property(np->parent, "assigned-addresses", NULL);
	if (reg == NULL)
		return;
	addr += reg[2];
	udbg_printf("final addr: %lx\n", addr);

	/* Setup for 57600 8N1 */
	addr += 0x20;
	sccc = (volatile u8 *) ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
	sccc += addr & ~PAGE_MASK;
	sccd = sccc + 0x10;

	udbg_printf("ioremap result sccc: %p\n", sccc);
	mb();

	for (i = 20000; i != 0; --i)
		x = *sccc; eieio();
	*sccc = 9; eieio();		/* reset A or B side */
	*sccc = 0xc0; eieio();
	for (i = 0; i < sizeof(scc_inittab); ++i) {
		*sccc = scc_inittab[i];
		eieio();
	}

	ppc_md.udbg_putc = udbg_putc;
	ppc_md.udbg_getc = udbg_getc;
	ppc_md.udbg_getc_poll = udbg_getc_poll;

	udbg_puts("Hello World !\n");
}

static int
cuda_init_via()
{
    int x;

    via[DIRB] = (via[DIRB] | TACK | TIP) & ~TREQ;	/* TACK & TIP out */
    via[B] |= TACK | TIP;				/* negate them */
    via[ACR] = (via[ACR] & ~SR_CTRL) | SR_EXT;		/* SR data in */
    eieio();
    x = via[SR];
    eieio();	/* clear any left-over data */
#ifndef CONFIG_MAC
    via[IER] = 0x7f;
    eieio();	/* disable interrupts from VIA */
#endif
    eieio();

    /* delay 4ms and then clear any pending interrupt */
    mdelay(4);
    x = via[SR];
    eieio();

    /* sync with the CUDA - assert TACK without TIP */
    via[B] &= ~TACK;
    eieio();

    /* wait for the CUDA to assert TREQ in response */
    WAIT_FOR((via[B] & TREQ) == 0, "CUDA response to sync");

    /* wait for the interrupt and then clear it */
    WAIT_FOR(via[IFR] & SR_INT, "CUDA response to sync (2)");
    x = via[SR];
    eieio();

    /* finish the sync by negating TACK */
    via[B] |= TACK;
    eieio();

    /* wait for the CUDA to negate TREQ and the corresponding interrupt */
    WAIT_FOR(via[B] & TREQ, "CUDA response to sync (3)");
    WAIT_FOR(via[IFR] & SR_INT, "CUDA response to sync (4)");
    x = via[SR];
    eieio();
    via[B] |= TIP;
    eieio();	/* should be unnecessary */

    return 0;
}

static void
fill_page_table_entry(page_table_entry *entry, uint32 virtualSegmentID,
	void *virtualAddress, void *physicalAddress, uint8 mode, bool secondaryHash)
{
	// lower 32 bit - set at once
	((uint32 *)entry)[1]
		= (((uint32)physicalAddress / B_PAGE_SIZE) << 12) | mode;
	/*entry->physical_page_number = (uint32)physicalAddress / B_PAGE_SIZE;
	entry->_reserved0 = 0;
	entry->referenced = false;
	entry->changed = false;
	entry->write_through = (mode >> 6) & 1;
	entry->caching_inhibited = (mode >> 5) & 1;
	entry->memory_coherent = (mode >> 4) & 1;
	entry->guarded = (mode >> 3) & 1;
	entry->_reserved1 = 0;
	entry->page_protection = mode & 0x3;*/
	eieio();
		// we need to make sure that the lower 32 bit were
		// already written when the entry becomes valid

	// upper 32 bit
	entry->virtual_segment_id = virtualSegmentID;
	entry->secondary_hash = secondaryHash;
	entry->abbr_page_index = ((uint32)virtualAddress >> 22) & 0x3f;
	entry->valid = true;
}

static void fsl_upm_end_pattern(struct fsl_upm *upm)
{
	clrbits_be32(upm->mxmr, MxMR_OP_RUNP);

	while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
		eieio();
}

/*
 * FIXME: This is only here to "make it work".  This will move
 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 * configuration library. -Matt
 */
static void __init
ebony_setup_pcix(void)
{
	void *pcix_reg_base;

	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);

	/* Disable all windows */
	PCIX_WRITEL(0, PCIX0_POM0SA);
	PCIX_WRITEL(0, PCIX0_POM1SA);
	PCIX_WRITEL(0, PCIX0_POM2SA);
	PCIX_WRITEL(0, PCIX0_PIM0SA);
	PCIX_WRITEL(0, PCIX0_PIM1SA);
	PCIX_WRITEL(0, PCIX0_PIM2SA);

	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);

	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);

	eieio();
}

static void scc_set_irq(ide_hwif_t *hwif, int on)
{
	u8 ctl = ATA_DEVCTL_OBS;

	if (on == 4) { /* hack for SRST */
		ctl |= 4;
		on &= ~4;
	}

	ctl |= on ? 0 : 2;

	out_be32((void *)hwif->io_ports.ctl_addr, ctl);
	eieio();
	in_be32((void *)(hwif->dma_base + 0x01c));
	eieio();
}

void
do_tlbie(union pte *pte, uval ptex)
{
	uval64 vsid,
	       group,
	       pi,
	       pi_high;
	uval64 virtualAddress;

	vsid = pte->bits.avpn >> 5;
	group = ptex >> 3;
	if (pte->bits.h) {
		group = ~group;
	}
	pi = (vsid ^ group) & 0x7ff;
	pi_high = (pte->bits.avpn & 0x1f) << 11;
	pi |= pi_high;
	virtualAddress = (pi << 12) | (vsid << 28);
	if (pte->bits.l) {
		virtualAddress |= (pte->bits.rpn & 1);
		tlbie_large(virtualAddress);
	} else {
		tlbie(virtualAddress);
	}

	eieio();
	tlbsync();
	ptesync();
}